SU1238221A1 - Converter of pulse sequence - Google Patents

Abstract

The invention relates to a pulse technique, in particular, to a pulse sequence converter having a single signal at the output, in the presence of a convertible sequence of pulses at the input. The purpose of the invention is to increase the switching speed and noise immunity of the output signal. The pulse sequence converter contains a counting trigger 1, input bus 2, two resistors 3, 4, capacitors 5, 6, diodes 7, 8, element OR 9. Elements NE 10, 11, element AND NOT 12, trigger 13 with control entrances. Using the invention improves the switching speed of the device with the end of the input pulses, since an accelerated switching of the device occurs, determined by the switching speed of the output trigger 13. The voltage and output pulsations are excluded, which is a source of interference. 2 Il. go from 00 th to th

Description

The invention relates to a pulse technique, in particular to pulse sequence converters, having a single signal at the output when there is a convertible pulse sequence at the input.

The purpose of the invention is to increase the switching speed and noise immunity of the output signal.

FIG. 1 shows a functional diagram of the converter; in fig. 2 is a diagram of the operation of the device.

The pulse sequence converter contains a counting trigger 1, the input of which is connected to the input bus 2, two resistors 3 and 4, capacitors 5 and 6, diodes 7 and 8, the element OR 9, the elements HE 10 and 11, the element AND NOT 12, the trigger 13 .

Direct and inverse outputs of the counting trigger 1 through resistors 3 and 4 are connected to the inputs of the element OR 9, which through capacitors 5 and b are connected to a common bus, parallel to each resistor 3 and 4 is connected a diode (7, 8), the anode to the input of the element OR 9, cathode - to the output of a counting trigger.

The input of the first element NOT 10 is connected to the input width 2, the input of the second element NOT 11 is connected to the output of the element OR 9, the outputs of the elements NOT 10 and 11 are connected to the inputs of the element AND-NOT 12, the output of which is connected to the control input. 13, the second control input. The setting in “1 flip-flop 13 is connected to the output of the HE element 11, the flip-flop outputs 13 are connected to the output buses.

The Converter operates as follows.

In the absence of pulses on the input bus 2 (Fig. 2a), the signal logical "1 is received from the output of the element OR 9 to the input of the logical element NOT 11. From the output of the logical element NOT 11 to the input of the logical element AND-NOT 12 and the input Set to "1 flip-flop 13 receives a logical signal" O. From the output of the logical element AND-NOT 12 to the input. Installation in “About the trigger 13 receives a logical signal“ 1. From the direct and inverse output of the flip-flop 13, the signals of the logical “O and“ 1 come to the output of the device.

Upon receipt of input pulses from the output of the element OR 9 to the input of the logical element NOT 11, a logical signal "O. At the output of the logical element 11, a signal of the logical "1 (Fig. 2e) is formed, which is fed to the input Set to" 1 flip-flop 13 and the input of the logical element AND-NOT 12. To the second input of the element AND-12, the inverted pulses of the input signal with output of the logical element NOT 10 (Fig. 2e) - From the output of the logical element NAND 12

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(Fig. 2g) negative input pulses are flip-flop trigger 13 on the input. Setting in “O. Thus, in the presence of input pulses at the input of the device, a logical "1 and logical" O signal is set at the direct and inverse outputs of the trigger 13. This eliminates output ripple, which occurs as a result of recharging capacitors 5 and 6.

 With the end of the input pulses to the input. Setting in "1 flip-flop 13" through element 11 enters a closed slice from one to zero of the output signal (Fig. 2e), which is formed as a result of recharging capacitors 5 and b with the ending of the input pulses. Input voltage Setting to "1 flip-flop 13 reaches the trigger threshold of flip-flop 13, which is reset to the initial state. On the direct and inverse outputs of the trigger 13

0 sets the logical signal "O and logical" 1.

Thus, when using the invention, the switching speed of the device increases with the end of the input pulses, since its accelerated switching occurs, which is determined by the switching speed of the output trigger 13.

Voltage and output ripples are excluded, which is a source of interference, therefore, noise immunity increases. 0

Claims (1)

Invention Formula A pulse sequence converter containing a counting trigger, two resistors, two capacitors, two discharge diodes, an OR element, an output bus and an input busbar with which the trigger counting input is connected, and the direct and inverse outputs are connected to resistors through 0 inputs of the OR element, which are connected via a capacitor to a common bus, a diode is connected in parallel to each resistor, an anode to the input of an Element OR, a cathode to an output of a counting trigger, characterized in that, in order to increase 5 switching speeds and noise immunity, two NOT elements are entered into it, the NAND element, a trigger with control inputs, the input of the first element is NOT connected to the input bus, the input of the second element is NOT connected to the output of the OR element, the outputs of the first and second elements are NOT connected to the inputs of the NAND element, the output of which is connected to the control input. Set to “About the trigger, second control input.” Setting to “1 is connected to the output of the second element, NOT, the trigger outputs are connected to the output buses of the device. a 5 in ishigigsh .J - J- gshshig gllllg -i t tpue.Z