SU1243121A1 - Pulse-width modulator - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in pulsed current and voltage regulators. The purpose of the invention is to improve the noise immunity and accuracy of the pulse-width modulator. To do this, a modulator containing an integrator 3, a bit transistor switch 5, a master oscillator 1, an inverter 2, a trigger 4, a comparator 12, a Uonof reference signal bus, an input bus signal, an output, common bus, resistors 10 and 11, and diodes 8 and 9, the second inverter .6, the NAND element 7. The introduction of new elements and connections made it possible to increase its noise immunity due to the arrival at the input of the comparator when the signals at its inputs are equal to a pulse signal from the trigger output, which prevents the comparator from chattering or his unstable Positioning the. When a device receives a very small signal at which there is no equality of signals at the inputs of the comparator, the duty cycle of the output pulses is forced by the clock pulse generator. The leading edge of the signal switches the comparator. This provides an increase in the accuracy of conversion of the input signal and stable operation of pulsed current and voltage regulators, limiting the maximum pulsed current. 1 il. With S (L dJmd GS Sttfoi Viifrofl

Description

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1243

The invention relates to the field of pulsed technology and can be used in pulsed current and voltage regulators.

The aim of the invention is to improve the noise immunity and accuracy of a flash-pulse modulator.

The drawing shows the block diagram of the device

1W} the rotary pulse modulator contains a master oscillator 1, an inverter 2, an integrator 3, a trigger 4, a bit transistor switch 5, an inverter 6, an element NE -2, a diode 8 and 9 - resistors 10 and 11, a comparator 12 The output of the reference generator 1 is connected to the input of the inverter 2 and the input of the discharge transistor switch 5 connected in parallel to the capacitor of the integrator 3, the input of which is connected to the input bus and the output to the anode of the diode 8 whose cathode is connected to the inverting input of the comparator 12, the cathode of the diode 9 and through a resistor 10 with a common busbar, The non-inverting input of the comparator 12 is connected to the reference signal bus, and its output is connected to the output bus and via a series-connected resistor 11 and inverter 6 to the installation input of trigger 1, the inverse output of which is connected to the first input of the NAND 7 element, the second input of which is connected to the output of the inverter 2 and the installation input to the O flip-flop 4, and the output to the anode of the diode 9.

The comparator 12 can be made on an operational amplifier, the integrator 3 can also be made on an operational amplifier, the output of which is connected to an inverting input through a capacitor, and a non-inverting input connected to an input bus through a resistor. The transistor switch 5 can be performed on a transistor. . the emitter and the collector of which are connected to the terminals of the capacitor of the integrator 3, and the base is connected via a resistor to the output of the master oscillator 1; Trigger 4 can be executed on a D-flip-flop, the D and S inputs of which are coy. Compressed via a resistor with a power bus, R-input - with the output of the inverter 2, and C-input - with the output of the inverter 6

Pulse width modulator operates as follows.

121 .2

When a positive pulse appears at the output of the master oscillator .1, the integrator capacitor is discharged. 3 through the included bit transistor switch 5 and the trigger 4 a negative pulse from the output of the inverter 2 is set in this way, its inverse output shows a high level, which ensures the formation of a negative differential on the falling edge of the pulse from the output of the inverter 2 at the output of the element AND-NOT 7 O Alternately, the differential switches the comparator 12 and thereby forms the leading edge of the output citro-modulated signal on the output bus. The charge of the capacitor 3 begins., And the steepness of its output voltage depends on the magnitude of the E.OT. signal,

The positive voltage from the output of the integrator 3 through the diode 8 is fed to the inverting input of the comparator 12, where it is compared with the reference signal. 11 and, the inverter 6 is fed to the input of the trigger 4 and sets it to G ". At the output of the element AND-NE 7, a positive n appears: a switch 5 which fixes the cross over of the comparator 12, then the process repeats and the arrival of the next pulse at the output of the master oscillator 1 ".

Introduction to the pulse-width modulator of new elements and connections made it possible to increase its noise immunity due to the arrival at the input of the comparator when the signals at its inputs are equal to a pulse signal from the trigger output, which prevents the comparator from chattering or its unstable triggering. In addition to TorOj, a very small signal arrives at the device input; there is no equality of signals at the comparator inputs; the duty cycle of the output pulses is set by the clock pulse generator, whose leading edge switches the comparator through the inverter connected in series and the IS element does not switch the comparator input and stability31

pulsed current and voltage regulators, limiting the maximum impulse current.

Claims (1)

Invention Formula A pulse width modulator containing an integrator, the input of which is connected to the input bus and parallel to the integrator's capacitor is a discharge transistor switch connected in series to a master oscillator and the first inverter, a trigger and a comparator, to the first input of which the reference signal bus is connected, differing in that, in order to improve noise immunity and accuracy, it is additionally available431214. The first and second resistors, the first and the second diodes, the second inverter and the NAND element are given, the anodes of the diodes being connected respectively to the outputs of the integrator and the NAND element, the first input of which is connected to the output of the first inverter and the input of the O device in the U trigger, and the second input - with the inverse trigger output, input 10 installation in 1 which is connected to the output of the second inverter, the input of which through the first resistor is connected to the output bus and the output of the comparator, the second input of which is connected 15 with diode cathodes and through a second resistor with a common bus, and the input of the discharge transformer switch is connected to the output of the master oscillator.