SU1152087A2 - Frequency divider - Google Patents

Abstract

DELITTAGE FREQUENCY on auth. St. No. 473306, characterized in that, in order to improve performance while simultaneously improving the output waveform by increasing the leading edge steepness, an additional capacitor, first and second additional resistors, an additional diode and an AND element, whose first input is connected to the input bus divider, and through the first additional resistor with a common bus divider, and the base of the transistor of the pulse generator through the second additional resistor connected to the input bus, the anode and cathode additional} south diode is connected respectively to the base and emitter of the transistor of the pulse bridge delay element, the collector of which is connected to the second input of the logic element I, the output of which is connected to the output bus of the bus (L tel, and an additional capacitor is connected between the base of the transistor of the pulse bridge delay element and the output inverter.

Description

The invention relates to a pulse technique and can be used in pulse frequency dividers. According to the main author, No. 473306, there is a frequency divider containing a pulsed bridge delay element with a voltage divider and a null organ in the diagonal of the bridge, a logic circuit. the output of which is connected to the inverter and the pulse generator, the resistive input of the logic circuit. The inhibit is connected to the output of the pulse generator, and the diode input to the output of the CO inverter. The disadvantage of this device is limited functionality Opportunities due to its relatively low speed, the unsatisfactory shape of the output impulse of a low steepness of its leading edge. The aim of the invention is to increase the speed while simultaneously improving the shape of the output impulse due to a decrease in the steepness of the front edge. The goal is achieved by introducing an additional capacitor into the frequency divider, the first and second additional resistors, an additional diode, a logical element AND, the first input of which is connected to the input bus of the divider, and the first additional resistor is connected to the common bus divider, and the transistor of the pulse generator through the second additional resistor is connected to the input bus, the anode and cathode of the additional diode are connected respectively to the base and emitter of the transistor of the pulse bridge element of the delay ki, the collector of which is connected to the second input of the logic element and the output of which is connected to the output bus of the divider, an additional capacitor is connected between the base of the transistor of the pulse bridge element of the bridge and the output of the inverter. . Figure 1 shows the circuit diagram of the device in .2, the ephors explaining the operation of the circuit. The device contains a pulse bridge delay element, made on a transistor 1, a capacitor 2, a resistor 3 with a voltage divider 4, a zero-body made on diode 5 in the bridge diagonal, a logic circuit that is made on the resistor 6 of the diode 7, for example diode, the output of which is connected to the input of a pulse bridge delay element, to the output of which the inverter is connected to the transistor 8 and the pulse generator of the transistor 9, the resistive input of the circuit is connected to the output of the pulse generator, and the diode input to the inverter output, additional capacitor 10, the first and second additional resistors 11 and 12, the additional diode 13, the AND 14 logic element, the first input of which is connected to the device input, and through the first additional resistor 11 - to the device common bus, through the second additional resistor 12 s the base of the transistor 8 of the pulse generator, the anode and the cathode of the additional diode 13 are connected respectively to the emitter of the transistor 1 of the bridge delay element, the collector of which is connected to the second input of the logic element 14, the output cat This is the device code, the additional capacitor 10 is connected between the base of transistor 1 of the pulse bridge delay element and the output of the inverter. The device contains. Also diode 15, the Device operates as follows. In the initial state, the transistor 9 is closed by zero bias at its base, the transistor 1 is also closed, the transistor 8 is open, the voltage on its collector is zero. The bridge circuit capacitor 2 is charged to the reference voltage through the open diode 5, the capacitor T0 is discharged, the diodes 7 and 15 are closed by reverse voltage at the junctions. At the first input of the logic element and TA Zero, at the second input of the Unit, at the output of the device signal Zero. When the first pulse arrives at the input, the transistor 9 and the bridge circuit capacitor 2 are discharged along the chain: diode 13, collector-emitter junction of transistor 9, resistor 6, diode 15. The duration of the input pulse is chosen from

to provide the full discharge time of the master capacitor 2 (Fig. 2 a).

During the input pulse, transistor 1 remains in the closed state, and transistor 8 in the open state. Since logical elements are acting on the inputs of the And 14 element, a pulse similar to the input one will be generated at its output (figure 2 d). After the end of the input pulse, the transistor 9 is closed and the charging process of the capacitor 2 of the bridge circuit begins. The loK charge is the base current of transistor 1, so the latter opens and forms Zero at the second input of the element 14. The transistor 8 at this time will be closed and the capacitor 10 will charge relatively quickly before the supply voltage, since its capacitance Dka hundreds of picofarads. The output signal from the collector of transistor 8 enters the diode one, the input of the Inhibit element, while the pulses from the collector of transistor 9 do not pass to the bridge delay element, since the diode 15 is closed by a negative voltage on its anode coming from the collector of transistor 8 through diode 7. As the voltage increases (Fig. 2b) on the capacitor 2 to the reference voltage, the charging current decreases and starts the process of locking the transistor 1 and unlocking the transistor 8. To force this process, positive feedback is introduced through Shelf capacitor 10. After this circuit

is set in the original state. From the principle of action it follows that negative impulses with steep fronts will form on the collector of transistor 1 (Fig. 2c). The coincidence of these pulses with the input pulses is recorded by the additionally introduced element I 14, at the output of which the pulse duration depends only on the source of the trigger pulses. Figure 2d shows pulses of the Prohibition in an idealized form, in practice there is a distortion of the fronts due to the presence of a capacitive load (capacitor 10). However, these distortions are minor and insignificant for the operation of the device.

Thus, a slight complication of the known device allowed to dramatically improve its characteristics. Due to the speed and independence of the output pulse shape from the parameters, the time it takes to close the circuit reduces the stability requirements for the delay time of the bridge element, since the locking process of transistor 1 can occur at any part of a given interval in the pause between input pulses.

At the same time, while ensuring stabilization of ve | | I ask || 0 {x parameters due to the qualitative selection of the bridge circuit elements in the proposed device, the division ratio can be significantly increased.

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Fig 2

Claims (1)

FREQUENCY DIVISER by ed. St. No. 473306, characterized in that, in order to improve performance while improving the shape of the output signal by increasing the steepness of the leading edge, additional I rn 4 5 solid capacitor, first and second additional resistors, an additional diode and logic element AND, the first input of which is connected to the input bus of the divider, and through the first additional resistor with a common bus of the divider, and the base of the transistor of the pulse generator through the second additional resistor is connected to the input bus, the anode and cathode of the additional diode are connected respectively to the base and emitter of the transistor of the pulse bridge delay element, the collector of which is connected to the second input of the logic element and AND, whose output is connected to the divider output bus, and an additional capacitor connected between the base of transistor bridge pulse delay element and the output of the inverter. YGG 'F