JPH0726980B2 - Peak detection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a peak detection circuit used in an oscilloscope or the like.

2. Description of the Related Art Conventionally, this type of peak detection circuit is realized by charging a capacitor through a diode connected to the input terminal. In addition, in order to compensate the output error due to the forward voltage of the diode, a circuit for comparing the input signal voltage and the output DC voltage is provided as shown in FIG. 4, and the capacitor for charging the capacitor by the output current of this comparator. Methods are also being considered.

FIG. 4 shows a conventional peak detection circuit. In FIG. 4, 21 is a comparator for comparing the input signal voltage with the output voltage, 22
Is a buffer amplifier with a sufficiently large input impedance.

When the input signal voltage is lower than the output peak voltage, the output of the comparator 21 is at a low potential, the diode is reverse biased, and the voltage across the capacitor, ie the output voltage, is preserved. When the input signal voltage becomes higher than the output peak voltage, the comparator 21
Goes high and the diode is forward biased, charging the capacitor until the output voltage equals the input signal voltage.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, the conventional peak detection circuit described above is intended for an input signal over the entire time domain, and it is not possible to detect the maximum (minimum) voltage of the input signal within a fixed time from an arbitrary time. It was impossible.

In addition, since the reverse current of the diode, the input current of the buffer amplifier, etc. actually discharge the electric charge of the capacitor, the output voltage decreases with time during hold, and it is not possible to detect the accurate peak value. there were.

The present invention solves such conventional problems,
It is an object of the present invention to provide an excellent peak detection circuit capable of accurately detecting the peak voltage of an input signal within an arbitrary period.

Means for Solving the Problems In order to solve the above problems, the present invention provides a comparator that compares an input signal with an output signal of a peak detection circuit and outputs a signal when the voltage of the input signal is high. , The output signal of this comparator, the gate signal, and the reset signal are input, the current source is connected to the capacitor by the logical product, the charging voltage of the capacitor is discharged by the reset signal, and the voltage of the capacitor is output by the peak detection circuit. The configuration is such that a buffer amplifier for signals is provided.

Operation According to the present invention, the peak value of the input signal is charged and held in the capacitor only while the gate signal is being input, and the peak value is reset by the reset signal.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, which is particularly aimed at detecting + peak. First
In the figure, 1 is a comparator, 2 is a current source, 3 is a switch circuit, 4 is a capacitor, 5 is a buffer amplifier, 6 is a logical product circuit, 7 is a reset circuit, and 8 is an inverter.

The above operation will be described. While the gate signal is "H" (positive logic), the switch 3 is closed and the input signal is compared with the output signal. As long as the input signal remains lower than the output signal, the constant current source 2 is driven to charge the capacitor 4. , The charging is stopped when they match, and conversely, the charged charge of the capacitor is held, that is, the peak value is held so that the output voltage becomes constant even if the input signal becomes a low potential.

When the gate signal becomes "L" (negative logic), the switch 3 is opened and the function as the peak detection circuit is stopped. The reset circuit 4 has a function of discharging the charge charged in the capacitor 4 at a constant cycle regardless of the gate signal.

FIG. 2 shows a specific embodiment of the present invention, and is intended for detecting + peak of an input signal whose minimum voltage is 0 V or higher. In FIG. 2, Q ₁ to Q ₆ are transistors, and transistors Q ₁ and Q ₂ and Q ₃ and Q ₄ form a balanced switching circuit, respectively. The base of the transistor Q ₁ is connected to the signal input terminal 11 and the base of the transistor Q ₂ is connected to the output terminal 14. The balanced switching circuit formed by the transistors Q ₁ and Q ₂ compares the input signal voltage with the output voltage. The base of transistor Q ₄ is kept at a suitable constant potential and its collector is connected to the common emitter of transistors Q ₁ and Q ₂ . Transistor Q ₅ has its base connected to the collector of transistor Q _{1 and} its collector a capacitor
It is connected to 15 and has the functions of the current source 2 and the switch circuit 3 in FIG. The transistor Q ₆ is a reset switching transistor whose base is connected to the reset input terminal 13 and whose collector is connected to the capacitor 15.
Reference numeral 17 is an output buffer amplifier having a sufficiently large input impedance. 16 is an inverter for inverting the signal polarity of the gate input terminal 12, D ₁ and D ₂ are diodes,
The diode D ₁ is connected to the output of the inverter 16 and the transistor Q ₃
Between the base of the diode D _{2 and} the reset input 13 and Q ₃
It is connected to the base of.

Next, the operation of the above embodiment will be described. In the above embodiment, the reset signal terminal 13 and the gate signal terminal 12 are both at the low level period, the diode D ₁ is “ON”,
Since the base potential of the Q ₃ becomes higher than the base potential of the transistor Q _4, the transistor Q ₄ is cut off. Therefore, no collector current flows in both the transistors Q ₁ and Q ₂ , and the base potential of the transistor Q ₅ increases, so that the transistor Q ₅ is cut off and the output potential is preserved.

During the period when the reset signal terminal 13 is low level and the gate signal terminal 12 is high level, both the diodes D ₁ and D ₂ are “OFF” and the transistor Q ₄ is “ON”. Therefore, the common emitter of the transistors Q ₁ and Q ₂ An electric current flows. Therefore transistor Q ₁ ,
The balanced switching circuit composed of Q ₂ compares the input signal voltage with the output voltage and controls the base potential of transistor Q ₅ . That is, when the input signal voltage becomes higher than the output voltage, the base potential of transistor Q ₅ drops and the capacitor
15 is charged by the collector current of transistor Q ₅ ,
Output voltage rises. Conversely, when the input signal voltage becomes lower than the output voltage, the transistor Q ₅ is cut off and the output voltage is preserved. By applying the pulse as the gate signal for a certain period in the non-reset state by the above operation, the maximum value of the input signal voltage within the certain period can be detected and held.

Further, when the reset signal terminal 13 is at the high level, the transistor Q ₆ is saturated, and the non-grounded terminal potential of the capacitor 15, that is, the output voltage becomes zero. At this time, the transistor Q ₅ is cut off.

FIG. 3 is an example of the timing of the input / output waveform when a repetitive pulse having a constant period T is applied to the reset signal terminal 13. Here, if the period T of the reset pulse is made sufficiently shorter than the discharge time constant of the capacitor during the peak voltage storage period, the output during gate open state is + when the reset pulse rises after the gate palace falls. The peak voltage is stored accurately. Furthermore, as long as the reset pulse satisfying the above conditions is applied, the accuracy of the output voltage during the peak voltage storage period can be guaranteed regardless of the temporal property of the gate pulse. Although the above example is directed to the side peak detection function, it is apparent that the side peak detection can be similarly realized by changing the direction of the current source, the polarity of the comparator, the discharge polarity at the time of reset, and the like.

As described above, in this embodiment, the switch circuit is controlled only by the output of the comparator while the gate signal is "ON" in the non-reset state, and its operation is the same as that of the conventional peak detection circuit. Also, while the gate signal is "OFF", the switch circuit is open regardless of the input signal, and the output voltage is saved. Therefore, it is possible to detect and hold the peak voltage of the input signal portion during the period when the gate output voltage is "ON", that is, the period when the gate is open.

Furthermore, during peak hold, that is, when the switch circuit is in the open state, a repeated reset pulse with a cycle sufficiently shorter than the time constant for discharging the capacitor is added to periodically charge and discharge the capacitor to a constant potential and output in the non-reset state. By taking out at an appropriate timing, it is possible to perform highly accurate peak detection with less output error due to discharge of the capacitor during peak hold.

This embodiment has the following effects.

(1) Since the charging current of the capacitor that holds the peak value is controlled by the input gate signal, the peak voltage of the input signal voltage within an arbitrary period can be detected by using an appropriate pulse signal as the gate signal. You can In particular, when a periodic pulse synchronized with the input signal for detecting the peak value is added as the gate signal input, one cycle of the input periodic waveform can be obtained by appropriately selecting the gate pulse width and the phase relationship between the gate pulse and the input signal. It is possible to detect the peak voltage in an arbitrary waveform portion within the.

(2) The reset signal waveform, the gate signal waveform, and the input signal are input by repeatedly applying a reset pulse with a cycle sufficiently shorter than the discharge time constant of the capacitor during the output voltage storage period and periodically discharging the capacitor to an appropriate constant potential. Regardless of the signal waveform and the time relationship between these three, it is possible to sufficiently reduce the decrease in the output voltage due to the discharge of the capacitor during the output voltage storage period, and to ensure the output accuracy at a certain level or higher.

Therefore, by using an appropriate reset pulse and an appropriate gate pulse that satisfy the above conditions, the peak voltage of an arbitrary input signal portion can be detected with a certain guaranteed accuracy.

As is apparent from the above embodiment, the present invention compares the input signal with the output signal of the peak detection circuit and provides a comparator that outputs a signal when the voltage of the input signal is high. A buffer that inputs the output signal, gate signal, and reset signal, connects the current source to the capacitor by the logical product, discharges the capacitor charging voltage by the reset signal, and uses the capacitor voltage as the output signal of the peak detection circuit. Since the amplifier is provided, the peak value of the input signal is charged and held in the capacitor only while the gate signal is being input, and the peak value is reset by the reset signal. It has an effect that the peak voltage can be accurately detected.

[Brief description of drawings]

FIG. 1 is a block diagram of a peak detecting circuit in an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the same embodiment, FIG. 3 is a timing waveform diagram of input / output signal type of the embodiment, and FIG. FIG. 4 is a conventional peak detection circuit diagram. 1 ... comparator, 2 ... current source, 3 ... switch circuit, 4
…… Capacitor, 5 …… Buffer amplifier, 6 …… AND circuit, 7 …… Reset circuit, 8 …… Inverter, 11 ……
Signal input end, 12 …… Gate signal input end, 13 …… Reset signal input end, 14 …… Output end, 15 …… Capacitor, 16 ……
Inverter, 17 …… Buffer amplifier, 21 …… Comparator, 22
...... Buffer amplifier, Q _{1 to} Q ₆ …… Transistor, D ₁ , D ₂
……diode.

Claims (1)

[Claims] 1. A comparator which compares an input signal with an output signal of a peak detection circuit and outputs a signal when the voltage of the input signal is high, an output signal gate signal of this comparator, and a reset signal are inputted. A logical product circuit that outputs the logical product, a switch circuit that connects a current source to the capacitor by the output signal of the logical product circuit, a reset circuit that discharges the charging voltage of the capacitor by the reset signal, and a voltage of the capacitor And a buffer amplifier that uses the above as an output signal of the peak detection circuit.