SU425331A1 - ADDRESS FORMER FOR DRIVER ON TIR STRUCTURES - Google Patents

Description

one

The invention relates to computing.

The characteristics of the storage device on the MIS structures determine the characteristics of the address driver as a device that provides switching modes (lagged, read) and output control pulses of the same polarity both in the write mode and in the read mode. In addition, the address driver must provide the necessary voltage drop regardless of the load, i.e., operate in a voltage generator mode.

Known address drivers for accumulators on MIS structures containing an input matching element, a voltage divider with active elements, a matching element of the mode, characterize a relatively long duration of the fronts of the generated pulses when going from one voltage level through zero to other voltage levels write and read modes; the dependence of the level of the generated voltage when reading on the parameters of the output key circuit (force factor, 1ko); large value of power consumption in the initial state; four power sources.

The purpose of the invention is to reduce the pulse duration at the transition from the

records to read, ensuring the stability of the levels of these pulses, reducing the power consumption in the initial state of the driver and saving equipment.

For this, the driver is equipped with a shunt transistor and a clamping diode, while the key transistor of the voltage divider is connected to the output of the input matching element through the C-chain and the emitter to the power supply through a resistor, in parallel with which the shunt transistor is connected to the power supply, the base of which is connected to the collector transistor matching element mode; the collector of the said key transistor is connected to the power supply of the opposite polarity and through the fixing diode to the output of the input matching element.

The drawing shows a schematic electrical diagram of the proposed driver for a drive on MIS structures. In the circuit of the proposed shaper, the key transistor 1 (pnp), which provides the formation of the write and read control pulses into the line, is connected via a C-chain containing resistor 2 and capacitance 3 to the base (p-p -p), which is the input matching element. The emitter of transistor 4 receives the control pulses of the address decoder, and its base is connected to ground via a resistor 0. The emitter of the key aransistor 1 is connected via a resistor 6 to a negative polarity power source - bp and through a resistor 7 to a collector of transistor 4. The collector of a key transistor 1 through a resistor 8 is connected to a power source of positive polarity + Un and through a fixed diode 9 to a collector of transistor 4 Parallel to the resistor 6 um, the shunt transistor 10 (pnp), the base of which is connected to the collector of transistor 11 (p -r), is turned on by an Iterno-collector junction, is its input, and is an element of the mode through it and through a resistor 12 - to negative polarity power source —Ep. The base of the transistor 111 through a resistor 13 is connected to ground. The input matching element transistor a 4 and the matching element of the transistor M mode are provided for matching the control inputs of the driver with integrated memory circuits. From the collector of transistor 1, the control write and read pulses are taken at the gate of a key MDPtransistor, which is not shown in the drawing, since it is included in the memory matrix of the MDP structures. . The proposed address shaper works as follows. In the initial state, the address line is under a positive potential equal to + En, since the key transistor 1 of the voltage divider is closed by a negative potential on the base, removed from the collector of the transistor 4, closed by the emitter of a low potential level. The transistor 10 is also closed by a negative potential on the base, taken from the collector of the transistor 11, which is closed by the low level of the potential emitter. Thus, in the initial state, all transistors of the circuit are closed, and power consumption is possible only along the circuit - {- En - resistor 8 - address line - author of the key MIS transistor. However, the MIS transistor, as a field-controlled element, has a very large input resistance and practically does not consume any current through the control circuit. In the recording mode, an impulse is formed in the address line with a difference from - {- En to -fWaan (-En). For this, a positive polarity pulse is applied to the emitter of transistor 4 from the address decoder. At the same time, the emitter of transistor 11 receives a positive write strobe from the local control circuit. Transistors 4, 11 open, the potentials of their collectors increase, and as a result, transistors 1, 10 open. At the same time, the latter shunts resistor 6. Thus, the address line is connected to -En through emitter-collector junctions of open transistors 1, 10. Total resistance the latter are much less than the resistance of the resistor 6. In the read mode, a pulse is generated in the address line with a difference from + Еп to --Ь / сснт (I С I Бп) and (I - Ссннт С I - Euse) For IT, a positive is applied to the emitter of transistor 4 impulse with descramble Dr. addresses; no recording strobe. As a result, the transistor 1 opens, and the transistors 10, 11 remain closed. As a result, the address line is connected to -En through resistor 6, and the potential (- count / address line) is determined by a voltage divider formed by transistor 1 and resistors 6, 8 connected between -En and + b / g. The divider reduces the voltage level in the read mode. By selecting resistor 6, the potential can be changed, which is determined only by the ratio of the divider arms and is not critical to the variation of the parameters of transistor 1, 10. In the write and read modes, resistor 2 and 3 / C capacitance reduce the duration of the leading and trailing edges formed pulses when going from one voltage level to another zero level. The inclusion of the collector resistance of transistor 7 in the emitter circuit of transistor 1 and clamping diode 9 in the collector circuit of transistor 1 helps to reduce the back, front of the generated pulse due to the early exit of transistor 1 from the saturation mode. In the proposed address shaper, the number of power sources is reduced to two. The address driver also saves RAM equipment, since shunt transistor 10, matching element 11 and resistors 6, 12, 13 can be implemented in one instance and is a common shunt circuit for all other key circuits of addressable AZR drivers . The proposed addressable driver is intended primarily for use in memory devices based on integrated circuits based on MIS structures. The subject of the invention. Addressable driver for accumulator MOS structures containing an input soldering element, a voltage divider with active elements and a matching mode element, characterized in that, in order to reduce the duration of the pulse fronts during the transition from recording to reading, to ensure the stability of these levels. pulses, reducing power consumption in the initial state of the driver and saving equipment, it contains a shunt transistor and a fixing diode, while the key transistor divider The base voltage through the RC-chain is connected to the output of the input matching element, the emitter - to the negative and 1 power source through a resistor.

parallel to which em.itter “on-collector junction is switched on shunt traisistor, the base of which is connected to the output of the matching element of the mode; the collector of the key transistor of the voltage divider is connected to the positive power supply bus and through a locking diode to the output of the input matching element.

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