SU1231505A1 - Device for checking electronic equipment - Google Patents

Abstract

The invention relates to computing and automation and can: be used in the automatic control systems of integrated circuits, as well as blocks and devices of discrete action during their production and operation. The aim of the invention is to improve the speed of the device. The device allows for each set of test sequences to reduce the number of interruptions in: the digital computer and the time spent on the organization of the interruption process. Set An electronic device monitoring device contains a trigger with a counting input, a clock generator, a switch, a pulse distributor, a comparison unit, a shift register, a counter, and a data preparation unit. 1 hp f-ly, 5 ill. § (L sd ate

Description

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ten

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The invention relates to computer technology and automation and can be used in systems for automatic control of integrated micro circuits, as well as blocks and devices of spurious action during their production and operation. The purpose of the invention is to increase the speed of the device.

Fig. 1 is a functional diagram of the device for controlling electronic devices; Fig 2 is the same as the pulse distributor; in fig. 3 - the same block comparison; n, and fig, 4 - the same, the data preparation block; FIG. 5 is a time diagram of the operation of the device.

The device for controlling electronic devices (FIG. 1) contains a digital computer (PC) 1, a trigger 2 with a counting input, a clock generator 3, a switch 4, a controlled device 5, a pulse distributor (CI) 6, a comparison unit 7, shifting register 8, counter 25 9, data preparation block 10, third 1 and tenth 12 outputs RIB, first 13 and second 14 outputs RI6, fourth 15, fifth 16, sixth 17, se, seventh 18, eighth 19 and ninth 20 RIB outputs, DZ output 21 stops of the process of control of the device, information output 22 of the device, installation input 23 y st-; devices.

The distributor 6 pulses (Fig. 2) 5 contains test 24, second 25 and seventh 26 elements AND, respectively, fifth element IL 27, second counting trigger 28, fourth element AND 29, second element OR 30, first element AND 31, first 33 , the third 34 and fourth 34 elements OR, the third 35 and first 36 counting triggers, respectively, the third element AND 37, the counter 38, the decoder 39, the eighth element AND 40, the sixth element OR 41, the second trigger 42, the tenth 43 , eleventh 44, twelfth 45 and nine 46 elements And, respectively, the first trigger 47 and fifth element And 48.50

Attracted 7 comparisons (FIG. 3) contains a register 49 and an equality circuit 50,

The data preparation block 10 (FIG. 4) contains the first register 51, the comparison circuit 52, the first element AND 53, 53 the first element OR 54, the error counter 55, the second switch 56, the decoder 57, the first switch 58, p:

40

45

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25 DA;

 5 50

53 2315052

Bistro 59, selector-multiplexer

60, the second 61 and the third 62 elements And the second element OR 63,

The input of the test sequence and the information output of the device are a p-bit code in accordance with the width of the selected digital computer,

The input and output of control object 5 is a code with the number of bits less than or equal to n.

The output of counter 9 is a k-bit code.

Switch 4 can be built on 2p two-input circuits AND (two cxeNtb AND one bit of information output of a digital computer), and the signal at the first (OUT, 1) and second (OUT, 2) outputs of the switch 4, respectively: em: OUT1-INF1 TG2; OUT2 “INF1 TG2, where ShF1 is a logical signal O or 1 i-th output of a digital computer;

40

45

bit information information TG2, TG2 - respectively, direct and inverse output signals of the trigger 2.

The device works as follows.

Before the start of operation, the signal supplied via communication line 23, trigger 2, clock generator 3, RIB and data preparation block 1 are set to the initial (zero) state. cycle, the timing diagram of the device for one set of test sequences is shown in Fig, 5,

When the first cycle is executed, DVM1 outputs to the object 5 of the control via the information channel the next set of test sequences. The output code of the monitored device 5 as a response to the sub input code is written into the register 49 of the block 7 comparison,

The first cycle starts at the start signal from the control output of the digital computer, which sets the trigger 2 to 1 and starts the clock generator 3, the output signal of the trigger 2 is the control signal for switch 4. From the information output of digital pulse digital signal 1, the next set of test sequence comes in, the Signal 1 from the output of trigger 2 is allowed to pass a set of test sequences to the input of the object 5j

3 .. control The output code of the monitored device 5 is fed to the register 49 of the comparator block 7.

The sequence of signals of the clock generator 3 through the element IZ 1 starts the counter 38, the signal from the first output of the decoder 39 participates in the formation of a signal in the communication line 1I controlling the writing of the output code of the monitored device 5 after the transients in it 49 into the register 49, as well as resetting the counter 38 and stopping the clock generator 3. This completes the first cycle.

When executing the second cycle, the reference code issued by CMV1 is compared, and the output code of the monitored device 5. Based on the comparison result, a code is generated, one in any of the bits of which indicates non-comparison for the given code bit of the control object and the reference code. for each bit with a value of I, starting at the youngest, an address code for that bit is generated and written to the data preparation block. After the formation of the data block for the digital computer is completed, an interrupt signal is output to it.

The second cycle also starts with the trigger signal from the control output of DVM1, which is at a time not less than 4 m from the first trigger signal, where T is the repetition period of the clock generator frequency 3. After a time less than or equal to T after the end

.The start-up signal of TsVM1 outputs from the information output to the switch 4

reference code. A trigger signal is set to O trigger 2 and is triggered; clock generator 3 is triggered.

When the output signal value of the trigger 2 is set to 0, the reference code through the switch enters the equality circuit 50 and is compared with the output code of the monitored device 5,

. arriving at equality circuit 50

 exit register 49.

The clock generator 3 generates a sequence of signals that trigger the counter 38, as a result of which the decoder 39 outputs a signal alternately at each of its outputs. The signal from the first output of the decoder 39 participates in the formation of a signal in link 13, according to which the code from the output of circuit 50 equality is being rewritten

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20, 25 30

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0 5

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in the shift register 8. The signal from the second output of the decoder 39 is set to 1 flip-flop 42, allowing the formation at the output of the elements I43, 45, 44 shifted one relative to the other sequences of the n signals. where n is the number of bits of the output code of the object 5 control.

Each signal in link 17 from the output of the I45 element under the condition of a single output of the shifting register 8 increases by one the state of the counter 55, and the corresponding output of the decoder 57 is a single signal controlling the selection of the register 59 for recording It has the output code of counter 9, which is the address code of the faulty bit. The moment the code is written into register 59 is determined by the signal on link 16 from the output of AND 44 passing through AND 62 under the condition of a single output of the shift register 8.

Each of the registers 59 contains K bits, where K for the limiting case when all outputs of the object: the controls do not match the reference code, is chosen from the condition

, n,

where K - the number of bits of the code issued by the information channel of digital computers. Since the case of a complete mismatch of bits is low, in practice the number of registers 59 can be reduced by 40-50% relative to the number n,

The signal from the second output of the decoder 39 has a duration equal to one period of repetition of the signals of the clock generator 3.

The signal from the third output of the decoder 39 sets in the trigger 47, blocking the start of the counter 38

- through the AND 31 element at the time of issuance, the sequence of n signals by the AND elements 43, 45, 44. After the completion of the output of the n signals from the output of the counter 9, the K 46-bit unit code arrives at the AND 46 element. When this signal 1 from the output of the element And 46 is set to the trigger 36. The signal from its output sets the triggers 42, 47 to O. At the same time, the output from the output of the elements And 43, 45, 44 is stopped and the blocking of the start of the counter 38 is removed. clock output5

pa 3, the signal from the third output of the decoder 39 is removed. In this case, the counter 55 records the number of all bits of one output of the comparison block 7, which have the value

By the signal from the fourth output of the depressor 39 through the elements of the IP 41, 63, the state of the counter 55 is increased by one.

By the signal from the fifth output of the decoder 39, the counter code 55 is written to register 51 and the interrupt signal is output to CMV1.

The signal from the sixth output deshifra1

the second output of distributor and cos - with the shift input of the shifting country and with the counting input of the device startup counter is connected to the 5 start of the clock generator, which is connected to the pulse clock of the pulse distributor, the first shape of the block input is compared to the information device of the controlled device 10, the distributor output pulses are not connected with a control input of a block of neni, the output of which is connected by an information input

Torah 39 counter 55 through the element ISH. The fS of the hist, different 54 is set to O. This completes the second cycle.

When the third cycle is executed, the generated data in the form of a set of the address code of the faulty bits on the 20th information channel is entered into the digital computer, then a stop signal is generated in the digital computer interrupt system, which, in order to verify the device’s operation, the T-trigger, the switch and a data wiring unit, the device start input is connected to the T-flip-flop counting house, the installation device is connected to the T-flip-flop input, the installation input generator and the first new inputs to distribute pulses and a preparation unit output 1 of the trigger is connected to the impulse distributor's throat input and the control input of the commutator whose information input is connected to the test sequence of the device, the first and second switching outputs of the switch are connected to the information input of the monitored device by the second information input b. the output of the pulse distributor is connected to the first stop of the clock generator; the fourth output of the pulse distributor is connected to the reset input; the output of which is connected to the input and the address of the faulty discharge data and with the input of the distributor code the pulsed, sixth, seventh, eighth outputs of the distributor are connected to the respective enable, second resolution of the counting, second installation and dark blue enable inputs of the cooking unit, the shift output of the register is connected to the input of the error The bits of the preparation block are given. The stopping block of the preparation block is connected to the second installation distributor of pulse pulses; the second stop of the clock generator is the output of the stopping process.

ca, evidence of the end of the exchange with the digital computer on this current set of test sequences. After that, DVM1 either analyzes the results or proceeds to the next set of test sequences.

The third cycle starts with the signal from the seventh output of the decoder 39, This signal blocks the start of the counter 38 and permits the passage of the counter 55 of the clock generator 3 through the AND 48, OR 41, 63 elements. In accordance with the counter code 55, the selector-multiplexer passes the line 22 communication code of one of the registers 59. When the codes of counter 55 and register 51 coincide, the comparison circuit 52 is triggered and the signal from the output of the element And 53 is zeroed through the element OR 54 of the counter 55, zeroed - the clock generator 3 and; RI6, and to the second interrupt input: CMV1, an ALARM signal is issued indicating the end of the process.

Claims (2)

1. A device for monitoring electronic devices, comprising a clock generator, a pulse distributor, a comparison unit, a shift register, a counter, the first output of the pulse distributor connected to the receiving input of the shift register, 31505 the second output of the pulse distributor - with the shift register shift input and with the counter input, the device start input is connected to the clock generator 5 input, the output of which is connected to the pulse distributor clock input, the first information input of the comparator unit is connected to the information output 10 of the monitored device, the third output of the pulse distributor is connected to the control input of the comparator unit, the output of which is connected to the information input of the shifter pefS, characterized gistra different The fact that, in order to keep the device fast, a T-flip-flop, a switch and a data preparation unit are inserted, the device’s start input is connected to the T-trigger counting input, the device’s setup input is connected to the T-trigger reset input, generator and the first set inputs of the pulse distributor and the data preparation unit, output 1 of the trigger is connected to the enable input of the pulse distributor and to the control input of the switch, whose information input is input the test sequence of the device, the first and second information outputs of the switch are connected respectively to the information input of the monitored device and the second information input of the comparison block. The third output of the pulse distributor is connected to the first input of the clock generator stop, the fourth output of the pulse distributor - to the reset input of the counter, the output of which is connected with the input of the code of the address of the faulty bit of the data preparation unit and with the input of the single code of the pulse distributor, fifth, more the seventh, eighth and ten outputs of the pulse distributor are connected respectively to the first enable, second enable, counting, second setup and third enable inputs of the dann cooking unit, the shift register output is connected to the error input in the bits of the data preparation unit, the stop output The data preparation unit is connected to the second installation input of the pulse distributor, the second stop input of the clock generator and is the process stop output. the device control, the information output of the data preparation unit is the information output of the device, the tenth output of the distributor, and; -pulses are connected to the fourth output; the input of the data preparation block and the output of the device interrupt signal, the data preparation block containing a comparison circuit, an error counter, a decoder, two switches, a selector-multiplexer, n + 1 registers, where p is the code the test sequence, three AND elements and two OR elements, and the reception input of the first register is the fourth permitting input of the data preparation block, the output of the first register is connected to the first input of the comparison circuit, the output of which is connected to the first the input of the first element AND, the output of which is connected to the first input of the lier element LRI and is the stop output of the data preparation unit, the second and third inputs of the first element OR are respectively the first and second installation inputs of the data preparation unit J the output of the first element OR is connected to the reset input of the counter error, the counting input of which is connected to the output of the second element OR, the first input of which is the counting input of the data preparation block, and the second input is connected to the output of the second element AND, the first input One of which is the second permissive input of the data preparation block, the error input in the bits of the data preparation block is connected to the second input of the second And element and to the first input of the third And element, the second input of which is the first permissive input of the data preparation block, the third output element I is connected to the control input of the first switch, the output of the error counter is connected to the information input of the first register, to the second input of the comparison circuit, to the information inputs of the second switch and the decoder, n output the decoder is connected to the group of information inputs of the first switch, the third enable input of the data preparation unit is connected to the control input of the second switch and to the second input of the first element I, the output of the second switch is connected to the control input of the selector-multiplexer, the information input group of which is connected with the outputs of the second (n + 1) -th registers, the first - the n-th outputs of the first switch are connected respectively to the inputs of the reception of the second - (n + 1) -th registers, whose information inputs form the input the address code of the faulty bit of the data preparation block, the output of the selector-multiplexer is yn. formation formatiox block preparation data. 2. The device according to claim I, wherein the pulse distributor comprises a counter, a decoder, three T-flip-flops, two triggers, six OR elements and twelve AND elements, with the first and second inputs of the first OR element being respectively the first and second elements the inputs of the pulse distributor, the output of the first SHS element is connected to the first input of the second SHSh element, the installation inputs of the first, second and third T-flip-flops by the first inputs of the third and fourth SHS elements and is the fourth outlet of the distributor pulses, the pulse input of the pulse distributor is connected to the direct input of the first element And, to the first direct input of the second element And and to the first inputs of the third, fourth and fifth elements And, the output of the fourth element I is the third output of the pulse distributor and is connected to the first the input of the fifth element SHS, the second input of the second OR element and the first inverse input of the first element AND whose output is connected to the counter input of the counter, the reset input of which is connected to the output of the second OR element, and the group of outputs with The sensor is connected to a group of inputs of the decoder, the first output of which is connected to the first input of the sixth And element and the second direct input of the second And element, the second, third and fourth outputs of the decoder are connected respectively to the first input of the seventh And element and with the first input of the sixth element OR, the fifth and sixth outputs of the decoder are respectively the tenth and eighth outputs of the pulse distributor, the seventh output of the decoder is connected to the second inverse of the first element And, second th input of the fifth elements 9 This AND is the ninth output of the impedance allocator, the output of the AND element is connected to the second input of the sixth OR element, the output of which is the seventh output of the pulse distributor, the first input of the ninth AND element is the input of the single code of the pulse distributor, the ninth output element I is connected to the counting path of the first T-flip-flop, the output of which is connected to the second inputs of the third and fourth elements OR and the inverse input of the eighth element AND, the output of which is connected to the S input of the first trigger, the R input of which is connected to the output of the fourth element OR, and the output of the first trigger connected to the third inverse of the input of the first element AND, the enable input of the pulse distributor is connected to the second input of the sixth element I and inverse inputs of the second and seventh elements AND, the output of the sixth element AND is connected to the second input of the fifth OR element, the output of which is connected to the countable input of the second T-flip-flop, the output of which 0 1505 ten connected to the second input of the fourth element And, the output of the second element And is the first output of the pulse distributor, the output of the seventh element And is connected to the S-input of the second trigger, H - the input of which is connected to the output of the third element OR, the output of the second trigger is connected to the right the input of the tenth element And with the second input of the third element And, the output of which is connected to the first inverse input of the tenth element And, the first input of the eleventh element And, the direct input of the twelfth element 5 And and the counting input of the third T-flip-flop, Exit is connected to the second inverted input of a tenth AND gate, BTopbws input of the eleventh AND gate and an inverted input of the twelfth AND gate, the outputs of the tenth, eleventh and twelfth AND gates are respectively second fifth and sixth distributor outputs pulses odinnad- output. The central element And is connected to the second input of the ninth element - that And 0 five (p.Vff. / tfae.t eleven / 2ts uh Thebes: 5