SU1226664A1 - Analog-to-digital converter - Google Patents

Abstract

The invention improves the performance of the analog-to-digital converter by reducing the duration of the coding cycle and eliminating errors such as incorrect switching on of the discharge or incorrect switching off of the discharge due to the use of beating measuring codes. In the mode of direct conversion of the input analog value to a digital code, a comparator unit, a digital-to-analog converter, a control unit, a voltage difference separator, a shift register, a block of OR logic units, a code scanner, and a code to minimize the form are involved. All units of the device are involved in the metrological control mode. The signal from the control unit records from one to the high-order bit of the code scanner, thereby ensuring that the high-order bit of the digital-to-analog converter is turned on. On the next signal, a sweep operation of the first bit of the digital-to-analog converter is performed. The voltage difference block performs a linear conversion of the first difference and the sum of the second and (digital-to-analog converter, where p is the parameter of the redundant measuring code used.) If this difference is exceeded, the differential difference block generates the sign of the unit in the first register. At the end of the first cycle, a code scanner is reset to the zero state. In the remaining cycles, the circuit operates in a similar manner. 1 Cp. F., 5 d., 2 tab. (L o S O) O) Od 4

Description

The invention relates to computing and digital measurement technology and can be used to convert analog values into digital ones.

The purpose of the invention is to increase the speed of the analog-digital converter.

Figure 1 shows the structural diagram of the analog-to-digital converter; Figures 2 and 3 show the firmware of the control unit; figure 4 - coded graph of the firmware; Fig. 5 is a functional block diagram of a control unit with forced addressing.

The analog-to-digital converter contains input bus 1, comparison unit 2 (BS), digital-to-analog converter 3 (DAC), voltage difference separation unit (REM) 4, shift register 6 (CP), block 5 of logical IDN elements (BLE OR), block 7

Communication designation

Purpose

1.1

1.2 2.1

2.2 3.1

3.2 3.3 4.1

4.2 5.1

5.2

5.3 6

7.1

7.2 8

BVR4 recording mode

BVR4 issue mode

Rg

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to

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RG ,,: R, (RG,)

BRK: o

  1 Oh. Scan

RG sync pulse: O

 1 RGtn About WEL control

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Reduction of the code to the minimum form (MF) MF (1-p): - O

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sweep code (BRK), register 8 (P), block 9 logical elements And (BLE I), block 10 bring the code to the minimum form (BPMP), block 11 of the control, information output tires 12, control output tires. 13. Block 5 of the logic elements OR contains the first inputs 14 and the second inputs 15 and 16. The device also contains the input bus 17 Operation mode, the Control unit 11 contains the first and second inputs 18 and 19, the third inputs 20, the first outputs 21, the sixth outputs 22 , the second outputs 23, the third outputs 24, the fourth outputs 25, the fifth input 26, the seventh output 27, the fourth input of the control unit 11 is the input bus 17 Operation mode.

Table 1 presents the micro-operations used in the microprogram (work of the analog-digital converter, clock).

Table I

connection

Communication number

21

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22

23

24 25

25 26

27

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The logical conditions used in the operation of the ADC are presented in Table 2,

table 2

Communication designation

Assignment of communication

Selection of operating mode: XI 1 - control mode XI О - direct conversion mode

X2

Analysis of block 2 comparison response:

X2 1 - A, X2 O - A.

Analysis of the state of the block L in the gap distribution: 19

KhZ 1-o .; ; -to.; ХЗ о - «p oi p 4od pfState of bits of the register РГ820

X4

X5

Cycle Counter State Analysis

X6

X6 1 if P1, p X6 Oh, if

The control unit 1 1 consists of a code analysis unit 28, a cycle counter 29, a multiplexer 30, a state decoder 31, a read-only memory (ROM) 32, a buffer register 33, a digital switch 34, and a clock generator 35. Code analysis block 28 is intended for the angles of register bits 8 for detecting the condition p, where p is a code parameter.

The digital-to-analog converter 3 must be built on the basis of redundant measuring codes, which include: p - Fibonacci codes, golden p-proportion codes, as well as generalized Fibonacci codes.

If the duration of the analog-to-digital bit conversion is chosen greater than or equal to

Communication number

17

18

Bx BX

1 - WG8 O

40

45

where t is the duration of the coding cycle of the analog-to-digital converter based on a binary code, then in this case the input (Ag) and the compensating (A) analog signals are balanced with an error not exceeding, for example, half of the lower-order DAC. If the duration of the cycle is chosen tj tf, then the balancing of A and the AI occurs incorrectly, due to the occurrence of type 50 coding errors, the wrong switching on of the discharge or wrong switching off of the discharge. For analog-to-digital converters containing a D / A feedback circuit 55, built on the basis of redundant measurement codes, the appearance of coding errors such as incorrect switching off of the discharge

does not cause a violation of the equality.

In order to exclude the type encoding error in the analog-digital conversion, incorrect inclusion of the bit in the process of balancing with the signal A introduces an asymmetry, which means that every C-m also has a bit-coded coding simultaneously with the tM bit C of the weight Qj include in the general case, a group of some lower-order bits with the sum of the weight of Idr. The value of AQ is determined by the formula

iQc

M

 Qrqe

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Based on the values, the K code is synthesized.

V aop

bits that are memorized. If the ratio is oi. between the weights of the bits of the code used is a constant number, then to form in the process of balancing on each subsequent j-th cycle of the code combination K; shift is made

jAon -.

source CODE combination one bit to the right.

The joint inclusion of B-th and the group of some lower-order bits causes the effective weight of the t-th bit to increase. Moreover, if the difference l A of the previous equilibration cycle was close to the value of the E-th digit, then in the current clock the comparison unit generates a logical signal causing the -th digit to turn off and further balancing is carried out by bits with numbers less than E

Thus, this approach makes it possible to eliminate type encoding errors and incorrect inclusion of the bit.

When converting an input analog value to a code with a device containing a DAC, built on the basis of a classical binary code with zero redundancy, such an asymmetry of the equilibration process is in principle impossible. In this case, an error of coding on a pa incorrect switching off of the discharge leads to the fact that the analog input value cannot be balanced by the signal Ac with an accuracy of the least significant bit LiAn. therefore

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the result of the conversion of A to the digital equivalent of K- is incorrect. If oyyh

To realize a digital-to-analog converter of the device on the basis of a redundant measuring code, then it is possible to carry out the correct analog-to-digital conversion in case of coding errors such as incorrect discharge switching off.

10 The introduction of asymmetry in the balancing process eliminates. type encoding errors wrong bit enable. All this makes it possible to significantly reduce

) 5 time of each j-th bit of a bit coding. In addition, on each tick of equalization, it is not necessary to carry out, for example, up to half the least significant bit, a comparison of the input A and the compensation A analog signals.

It is enough to allocate the time required for establishing transition processes in the DAC and the comparison unit with an error of not more than SQ for one step of the bit balancing. The SQ value depends on the redundancy of the code that is used in the DAC, and. is determined by the formula

30 8q 2cc - 1.

I

where oG is the ratio between the adjacent members of the code on the basis of which the DAC is built. .

For the Fibonacci number with, for example, (o; 0.61803) the error B Q, expressed in%, is 6Q 23.6%.

The operation of the analog-digital converter occurs in the mode of metrological control and in the mode of direct conversion of an analog value into a digital code.

The process of metrological control determines the presence of failed bits in the device, the numbers of which are entered into the register 8. A failed bit or a bit whose weight does not correspond to the required value is considered to be failed.

In the mode of direct conversion of the input analog value to a digital code, a comparison unit 2, a digital-analog converter 3, a control block 11, a block 4 for voltage difference separation are involved. Shift register 6, block 5 logical elements OR and block 7 scan

35

40

45

50

55

code, block 10 code reduction to the minimum form.

All units of the device are involved in the metrological control mode. The metrological control of the analog-to-digital converter is carried out on the basis of certain ratios between the weights of the digits of the digital-to-analog converter implemented in codes with an irrational basis (Fibonacci codes and golden p-propordia codes).

In the metrological control mode, in the first cycle, the unit of the control unit 11 records the unit to the high bit of the code scanner 7, thereby enabling the high bit of the digital-to-analog converter 3 to turn on. The following signal performs the scanning operation of the first digit of the digital-to-analog converter 3. Block 4 isolating the voltage difference performs a linear transformation of the difference between the first and the sum of the second and (p + l) -th bits of the digital-to-analog converter 3. In case of this difference, the value and the allowable limit of the voltage difference allocating unit 4 produces a sign of the unit being written to the first digit of the register 8. At the end of the first clock cycle, the code sweep unit 7 is reset. In the second cycle, the control unit 11 records the unit is the second bit of the code scanner unit 7, thereby enabling the second bit of the digital-to-analog converter 3 to be turned on. Next, the second-stage scan operation of the digital-to-analog converter 3 is performed. In the first cycle, the voltage difference extracting unit 4 produces a corresponding. signal supplied to control unit 11. In the remaining (n-2) cycles, the circuit operates in a similar way, ensuring the sequential switching on and development of the remaining-. c (n-2) bits of the digital-to-analog converter, as well as checking - the ratios

J. (O

If block 4 is triggered for the first time on the i-M clock cycle, then the i -th and bit of the register 8 is set to one, and the remaining bits are zeros. .If a.

The voltage difference allocating unit 4 is triggered at the (i + 1) cycle, then a unit is recorded in the (1 + 1) -th bit of register 8, and a zero is recorded in the i -th and bit. The writing of the unit to the subsequent bits and zeros in the foregoing bit occurs until block 4 of the differential voltage difference,

The termination of the operation of block 4 indicates that ratio (l) is fulfilled. Thus, the numbers of the degraded bits appear in the register. If there are failed bits, the metrological control ends by checking whether the input value can be correctly converted to a digital code. If in the process of metrology

control detected failed bits, whose numbers; entered in register 8, then in the process of balancing the input analog signal Ag with a compensating signal A |

the inclusion of these bits prohibits- The coding is performed only with good accurate bits.

An analog-to-digital converter correctly converts an input analog value to a digital code, if after each group of m (I mg P) there are more or less located failing bits, at least m +1 lower exact bits follow or there is no more than one group of ha () failed bits

However, the balancing of the k by the compensating DAC signal in the presence of failed bits must be carried out using a slow algorithm. At that, in the register 6 the code combination is entered, all bits of which are equal to zero. In the case of

the accelerated algorithm, the result of the analog-to-digital conversion may be incorrect due to the loss of redundancy of the CAPP due to the presence of failed bits. If there are no failed bits in the ADC, the coding is carried out using an accelerated algorithm. In this case, the analog-digital conversion occurs as follows. At the first step of converting the input analog value Ag, to the code Kgy, the signal of the control unit 11 is set to the unit state

block 7 scan code, and in the shift register on the signal of block 1 of the control is set code combination Cdop ,.

Through block 5 of the logic elements OR, the code combinations K and Cd of the outputs of the shift register 6 and block 7 of the code sweep are fed to the input of DAL 3, at the output of which appears the compensating analog signal Aj (, (Q, + Qдon,), where Qf ,. , is the weight of the older bit of the CDP.

The comparison of the compensating analog signal A k to the input analog signal A is made using the comparison unit 2. Moreover, the output signal YJ of this block obeys the following relation

Sje

s

if ap ahh if a g

In this case, if on the first step of equilibration Y O, then the (n-1) -th bit is set to the zero state, but if Y 1, then (n-1) - the bit is set to one state.

In the second analog-digital conversion cycle, the signal of control unit 1 shifts the content of block 6 by one bit to the right, resulting in the output of the shift register with the code KdO2 at the same time (n-2) th bit of scanner 7 The code is set to one. At THIS, a compensating signal AH-appears at the output of the D / A converter 3. Depending on the result of comparing the output A and the compensating A analog signals, the (p-2) -th bit is set either to the zero state (Yj O) or remains in the single state (Yj). The operation of the analog-digital converter on Any tact is similar. The direct conversion process ends in a (n + 1) -th bit of the bit-coded coding. At the same time, the input signal, the signal, Ard is balanced by the compensating signal of the DAC A, with an accuracy of 1 DAC Z.

The result of the conversion, generated in the code sweep block 7, is fed to the minimum form block 10, after which

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Informational output bus 12 device enters a code presented in minimal form.

Claims (2)

Invention Formula A 1-analog-to-digital converter containing a comparison unit, the first input of which is an input bus, the second input combined with the information input of the voltage difference separator and connected to the output of the digital-to-analog converter, and the output connected to the first input of the control unit, the first outputs of which connected to the control inputs of the voltage difference block, the output of which is connected to the second input of the control unit, the second codes of which are connected to the first information inputs of the code scanner, the third outputs are connected to the control inputs of the code scanner, the outputs of which are connected to the corresponding first information inputs of the AND block, the second information inputs of the code scanner are combined with the corresponding second information inputs of the AND block, the third inputs of the control block and connected to corresponding outputs of the register, the inputs of which are connected to the fourth outputs of the block, the control, the fifth output of which is connected to the control input of the block x elements AND whose outputs are control output buses of the converter, characterized in that, in order to improve performance, a block of logic elements OR, a block to reduce the code to the minimum form, a shift register, the inputs of which are connected to the sixth outputs of the control block, and outputs are entered into it - to the corresponding first inputs of the OR block of logical elements, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter, the second inputs are combined with the corresponding information inputs and the block code to actuate the minimum shape and are connected to corresponding outputs code scanner, driving unit outputs, to the minimum code form information are output lines transducer under the control inputs Connected to the seventh outputs of the control unit, the fourth input of which is a bus. Operating mode. 2. The converter according to claim 1, characterized in that the control unit is executed on a multiplexer, code analysis unit, counter, decoder, register, digital switch, clock generator, permanent memory, whose inputs are connected to the corresponding outputs of the digital switch and the outputs to the corresponding information inputs of the register, the control input of which is connected to the output of the clock generator, the outputs from the first to the eighth are connected to the corresponding inputs of the decoder, the outputs from the virgins to eleventh - to the corresponding control inputs of the multiplexer, outputs twelfth to sixteenth - to the corresponding first information inputs of the digital switch, outputs seventeenth to the twenty-first, are connected to the corresponding second information inputs of the digital switch that controls 1226664 12 the input of which is connected to the output of the multiplexer, the first, second and third information inputs of which are respectively the fourth, first and second inputs of the control unit, the fourth and fifth inputs are connected respectively to the first and second outputs of the code analysis unit whose inputs are the third inputs the control unit, the sixth input of the multiplexer is connected to the output of the counter, whose input is connected to the first output of the decoder, the second and third outputs of which are the first outputs of the control unit, the fourth and the fifth outputs of which are the sixth outputs of the control unit, the sixth, seventh and eighth outputs by the second outputs of the control unit, the ninth and tenth outputs by the third outputs of the control unit, the eleventh, twelfth and thirteenth outputs by the fourth outputs of the control unit, the fourth the output is the fifth output of the control unit, the fifteenth and sixteenth outputs are the seventh output of the control unit. ABOUT) (Price is "Utt-l . . - .five Compiled by V.Pershikov Editor A.Sabo Techred: V.Kadar Proofreader A.Ferents Order 2147/59 Circulation 816 Subscription VNIIPI of the USSR State Committee for Inventions and Accidents 113035, Moscow, Zh-35, Raushsk iab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4