SU1381699A1 - Device for calibrating testing of digital-to-analog converters - Google Patents

Abstract

The invention relates to digital electrical engineering and can be used in measurement information systems. The goal is to increase accuracy and speed. The device contains a rotatable digital-analog converter 1, an analog storage device 2, an analog subtraction unit 3, an analog-digital converter 4, an arithmetic unit 5 executed on a register 6 and a digital subtraction unit 7, a control unit 8 executed on a clock generator 9, the counter 10 and the decoder 11, the accuracy and speed is obtained by introducing the arithmetic unit 5 and changing the connections of the analog storage device 2. 2 Cp f-ly, 1 ill. (L

Description

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The invention relates to digital electrical engineering and can be used in measurement information systems.

The purpose of the invention is to improve the accuracy of speed II.

The drawing shows a functional diagram of the device for checking digital-analog converters.

The device for checking digital-to-analog converters contains a rotatable digital-to-analog converter 1 (CGT), an analog storage device 2, an analog subtraction unit 3.1 performed on register 6 and a digital subtraction unit 7, control unit 8 executed on a clock generator 9, counter 10, the decoder 11.

The device works as follows.

The input buses of the DCL 1 being turned on are connected to the first output buses of the device, and the output of the DAC 1 is connected to the flow of the device. Let it be required to determine the differential nonlinearity when changing the code N to the code N, N I + 1. First, block 8 supplies the inputs of the CLP 1 with the code N, which is converted to the voltage U ,. By block 1 of block 8, the analog storage device 2 stores the voltage Uj, and the voltage U appears at its output (U U due to the imperfect analog storage device 2). At the command of block 8, analog-to-digital converter 4 outputs the output voltage of the unit.

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and, and in the NJ code,

N carries information

which is written in register 6. Code

about the error analog storage device 2, block 3 and analog-to-digital converter 4. Then block B feeds a code N to the DAC 1, which is converted to voltage & U. At the command of block 8 analog-digital converter 4 converts the output voltage unit 3 is equal to 4U

 and

in the NJ code. At the output of the digital subtraction unit 7, the code N NJ - N is formed. The N code is free from the systematic additive components of the errors introduced by blocks 2-4 and petet in itself information about the voltage increment at the output of the DAC 1 when the code is at its inputs ( at NN, + 1 code N is proportional

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Claims (3)

1. A device for calibrating digital-to-analog converters containing a control unit whose output group is the first output bus, the first output is connected to the control input of the analog storage device, the output of which is connected to the first input of the analog subtraction unit, the second input of which is input bus, the output to the information input of the analog-digital converter, which differs from the fact that, in order to improve accuracy and speed, an arithmetic unit was introduced, the information input of which It is connected to the output of the analog-digital converter, the output is the second output bus, the control input is connected to the second output of the control unit, the third output of which is connected to the control input of the analog-digital converter, while the information input of the analog storage device is combined with the second input analog subtraction unit. 2. The device according to claim 1, wherein the arithmetic unit is executed on a register and a digital subtraction unit, the first input of which is combined with the information input of the register and is an information input of the arithmetic unit The register input is the control input of the arithmetic unit, the output is connected to the second input of the digital subtraction unit, the output of which is the output of the arithmetic unit. 3. The device according to claim 1, characterized in that the control unit is made on the decoder, counter and clock generator, the output of which is connected to the clock input of the counter, the outputs of the higher bits of which are the group of outputs of the block, the outputs of the lower bits are connected to the corresponding the inputs of the decoder, the first of which is the first output of the block, the second output is the third output of the block, the third output is the second output of the block.