SU1223368A1 - Analog-to-digital converter - Google Patents

Abstract

The invention relates to computing and digital measurement technology and can be used to convert analog values to digital ones. It allows to increase the accuracy of the conversion due to the use in the analog-to-digital converter (ADC) of bitwise coding of redundant measuring codes (nickname). The construction of a digital-threshold converter on the basis of the KII, as well as the introduction of the first and second blocks of the OR elements, the second block of the AND blocks, the second scanner of the codes, the second register, the fixed memory block and the clock generator, allow an accelerated metrological self-checking of the ADC worsening the speed of the ADC in the mode of conversion of the input signal, which provides an increase in the reliability of the conversion. 2 hp f-ly, 4 ill. (L

Description

one

The invention relates to computing and digital measurement technology and can be used to convert analog values to digital ones.

The purpose of the invention is to increase the reliability of the analog-digital converter,

.In FIG. 1 shows the functional diagram of the analog-digital converter (ADC); in fig. 2 is a functional block diagram of the control unit; in fig. 3 and 4 is a graph-diagram of the algorithm of the device.

Analog-to-digital converter contains input bus 1, comparison unit 2, digital-to-analog converter 3 (D / A converter), second register 4 (2РГ), first code scanner unit 5 (1БРК), first unit 6 of elements OR, second unit 7 of elements OR second unit 8 elements I (1BLE I), the second block 9 sweep codes (2BRK control unit 10, generator. 11 that clock pulses, advantageous information bus 12, Output control P-bus 13. Control unit 10 contains outputs 14-22 from first to nine the first and third inputs 23-25, the ADC also contains the first block of elements 26 and the first register 27 (1RG).

The control unit 10 (Fig. 2) is made on the first and second registers 28 and 29, the inverter 30, a permanent storage device 31 (ROM).

A digital-to-analog converter (D / A converter) 3 should be built on the basis of a redundant measuring code (IIC), for example, the Fibonacci code or the golden ratio. Analog-to-digital converters, built on the basis of redundant measuring codes, have the ambiguity of the output characteristics, which allows monitoring of their metrological characteristics. The basis of the control is the presentation of one analog value by different code combinations and the comparison of the latter with each other. In this case, if the weights of bits A1ch do not have deviations from the required values, then one analogue equivalent will correspond to these code combinations. If the weights of bits A1C have deviations from the required values, then different code combinations

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various analogue equivalents will match.

This circumstance underlies the control of the proposed analog-to-digital converter. Moreover, various code combinations: necessary for monitoring are obtained by balancing the input signal with different durations of the 10 coding cycle.

It is known that for an ADC constructed on the basis of a non-redundant binary code, there is a minimum possible tact time of 15 times a decoding coding, where the analog-to-digital conversion will be carried out correctly. The value of t. - provided that the output of the D / A converter is set

20 exponentially determined by

PE, -. (+ B

where € is the time of the DAC;

n is the number of cycles of bitwise encoding. If the duration of the bit code encoding is less than the value of tj; then it is possible that

the balancing will not be correct due to the occurrence of balancing errors such as incorrect switching on of the discharge.

For analog-to-digital converters containing DACs in the feedback circuit built on the basis of redundant measurement codes, due to the presence of redundancy in the latter, the occurrence of coding errors such as incorrectly switching on the discharge will not cause unbalanced hanging of the input signal Аg by a compensating DAC signal A.

In order to exclude the analog-digital conversion

the type encoding error, the improper activation of the discharge in the process of balancing A with the signal A introduces an asymmetry,

that at each if-M bit of a bit encoding simultaneously with the th bit with a weight of 0, g includes a group of some of the least significant bits of total weight LO.dop. The value of l Q., on is determined by the formula 6-

.

ten

Based on the values of 1, a low-order Kg code is synthesized, which, when the device is manufactured, is entered into a block of the permanent memory.

If the ratio between the weights of the bits of the code used is a constant number, then in order to form, in the process of balancing, on each subsequent J-M cycle of the code combination, the source code is shifted

combinations of kn for one bit of apr AO VO.

The joint inclusion of the 1st and the group of some of the least significant bits causes the effective weight of the 1st digit to increase. In this case, if the difference, at the end of the preceding tact, the balance was close to the value of the 1st bit, then in the current cycle the comparison unit will generate a logical cash, causing the 1st bit to be turned off and further balancing will be performed with bits with numbers less than 1.

In this way, type encoding errors are prevented from incorrectly turning on the bit.

When converting an input analog value to an analog-to-digital converter code containing

A DAC built on the basis of a non-redundant binary code, such an asymmetry of the balancing process is in principle impossible. In this case, a coding error incorrectly turning off the bit will result in the input analog value Aj not being able to balance the signal A to within the smallest bit of the DAC. Therefore, the result of converting Ag to the digital equivalent of Kjb will not be valid. If an analog-to-digital converter is implemented on the basis of a redundant measuring code, then it becomes possible to perform the correct analog-to-digital conversion in case of coding errors such as incorrect discharge off. The introduction of asymmetry in the balancing process eliminates the type encoding errors of the improper inclusion of the discharge.

These circumstances can significantly reduce the time of each

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th j-ro clock bit of a coded coding. At the same time, on each tick of the equilibrium, there is no need to make accurate, for example, up to half of the youngest bit, the comparison of A and the compensating A analog signals. It is enough to allocate the time necessary for establishing transient processes in the DAC and the comparison unit with the SQ error for one step of the bit balancing. The value of SQ depends on the redundancy of the code on the basis of which the DAC is built, and is determined by the formula

 ,

where tf is the relationship between neighboring members of the code on the basis of which the DAC is built.

20 For Fibonacci numbers with (oi 0.61803 ...), the error Q, expressed as a percentage, will be equal to Q 23.6% ..

So building a DAC,

25 based on the KII and a small measurement of the Heitne bitwise coding algorithm allows to produce the correct analog-to-digital conversion with a significant decrease

30 coding cycle duration in relation to the nominal value. This circumstance is used to control an analog-to-digital converter.

35 The operation of the device occurs in

direct conversion of the input signal to the code in two cycles. Moreover, the duration of a single bit of a single encoding in the first

The 40th cycle is equal to t, (t,), and the duration of one clock cycle of bitwise encoding in the second cycle is equal to tjCtj tTj;).

In the first cycle, the conversion of the input analog value into a code is performed by the classical bit-wise roving method using blocks 2, 3, 4, 16, 6, 10 and 11, with the second register 4 being in the zero state during the entire coding cycle.

The comparison of the compensating signal A and the analogue input signal of the AI is carried out with the aid of a comparator unit 2, the output signal Y: of this unit obeys the following relation

t ,,, ь

if A. „And I .;

A °. J

if Aft, A, j.

The encoding process ends on the nth time step of the encoding. At the same time, the input analog signal Ag is balanced by the compensating signal of the DAC 3 with an accuracy of half the least significant bit of the DAC 3 and on the output information buses 12 of the device, the K code (which is the digital equivalent of the input analog signal Ag

At the (n + 1) -th cycle, the K code is written, from the first register 26 to the second code sweep block 9 and the signal of the control block 10 of the control variable frequency oscillator 11 changes the frequency of the driving pulses from ff. on f.

In the second cycle, on the first step of converting the input analog value of A c to the Kg code according to the signal. the control unit 10 is set to one state (the pth bit of the first register 27 and the second combination 4 records the code pattern Cdd, which goes to the first block 6 of OR logic elements. Then the code combinations through the first block 6 logical elements OR are fed to the input of the DAC 3, the output of which is VITs, which compensates the analog signal A, Q ni + 0lop, 1, where 0. n – 1 is the weight of the senior bit of the DAC.

The comparison of the compensating signal A | (, and the input analog signal A g is carried out with the help of the comparison unit 2.

In the second analog-digital conversion cycle, the signal of the control unit 10 is shifted by the contents of the second register 4 by one bit to the right, with the result that the code combination CDr ",. At the same time, the (p-2) -th bit of the first register 27 is set to one. At the same time, at the output of the DAC 3, a compensating signal A is output.

The operation of the device at any j-th cycle is similar. In the first register 27 is set to the single state (n -) - th bit, the contents of the second register 4 is shifted by one bit to the right, with the result that at the output of the second re

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the horn 4 is in accordance with the WCD code pattern Cdd ,,, and the output of the DAC 3, in turn, is the compensating analog signal AC, which is compared with the signal J in A of the CK using the compare unit 2. On a signal Y (n -) - i bit, either remains in a single state or is set, to well (Y-1)

left state ()

10 The encoding process ends on the nth bit of the bit encoding. At the same time, the input analog signal A gj is balanced by the compensating signal A. The D / A converter 3 with an accuracy of up to half the least significant bit also on the output information buses 12 of the device, according to code K, which is the digital equivalent of the input analog signal A. On

20 (p + oh tact) the code K is written from the first register 16 to the first block 5 of the code sweep.

Above the contents of the blocks 5 and 9 times the screwing of codes completes the operation

25 subtraction. The first code scanner 5, the second code scanner 9, the second And block 8 and the control block 10 are involved in generating the difference of the code combinations. The completion of the subtraction operation is performed by scanning the code combinations in the first code scanning block 5 and in the second code scanning block 9 and setting the zero state to 25 matching significant bits of the code, and setting the zero state to the same bits after the full code scan. This process occurs before the zero code combination is submitted, at least in one of the code scanners. The appearance of the zero code combination is the absence of coincidence signals of significant bits

45 code coming from the output of the second block of 8 logical elements I.

After performing the subtraction operation, the contents of one of the blocks 5 or 9 through the second block of 7 elements

50 OR and the first block 26 of the AND logic elements, in the presence of an enabling signal from the control unit 10, is fed to the control output buses 13 of the device. The presence of a non-zero code at the control output 13 indicates the presence and magnitude. no deviations of the weights of the DAC bits from the required values.

Control unit 10 can be synthesized by various methods. For example, it can be implemented on the basis of a memory machine or on the principle of programmed control.

One possible implementation of the control unit is shown in FIG. 2. For the generation of control signals, a sequential circuit using a ROM is applied.

The necessary for controlling the operation of the A1JJI control and conventional signals are given in the table.

The operation algorithm of the device in accordance with the above description of the operation for is shown in FIG. 3 and 4.

The algorithm consists of vertices:

1.v.1-17 - resetting 2RG and balancing the input analog value at t

2

2.В.18 - change in frequency Г с

f to fp in 2RG rewrites an additional code combination from the BHT and the contents of 1RG are rewritten in 2BK;

3.ev.19-35- balancing of the input analog value at t it-, "";

4.iv.36 - is being rewritten in 1BRK

contents of 1RG;

5.B.37-39- the subtract operation is performed by setting the matching significant bits of the code to the zero state;

6.b.40 - resolution signal for

receipt of information on the control output.

Claims (2)

1. An analog-to-digital converter containing a comparison unit, the first input of which is the input length, the second input is connected to the output of the digital-to-analog converter, the control unit, the first output of which is connected to the control input of the first register, the outputs of which are connected to the corresponding first information the inputs of the first code scanner, the first and second control inputs of which are under 223368 Switched respectively to the second to the third outputs of the control unit, the fourth output of which is connected to the first input of the first block of elements J and whose outputs are output control tires, characterized in that, in order to increase the reliability of the conversion, the first and second 0 blocks of OR elements, the second block of the AND gates, the second scanner of the codes, the second register, the permanent memory block, the clock generator, whose input is connected to the top of the control unit, and the output to the first input of the control unit, the sixth, seventh and eighth outputs of which are connected respectively to the first, second and third control 2Q inputs of the second register, informational inputs of which are connected to the corresponding outputs of the block of permanent memory, and outputs to the corresponding first inputs of the first block 25 OR elements, whose outputs are connected to the corresponding inputs of the D / A converter, the second inputs are combined with the corresponding first information inputs of the second scanner of codes and connected to the corresponding outputs of the first register, which are the output information buses of the first control input of the second scanner of the codes connected to the ninth output of the control unit, the second control input is combined with the second control input of the first scanner of the codes, and the second information input e inputs are combined with the corresponding second information inputs of the first scanner of the codes, second inputs of the control unit and connected to the corresponding outputs of the second block of AND elements, the first 5 inputs of which are combined with the corresponding first inputs of the second block of OR elements and connected to the corresponding outputs of the first scanner of the codes, and the second inputs 0 are combined with the corresponding second inputs of the second block of the OR elements and are connected to the corresponding outputs of the second scanner of the codes, the output The sys- tems of the second block of elements 5 OR are connected to the corresponding second inputs of the first block of elements AND, while the information input of the first register is connected to the output of the block 30 0 at comparison, and the third input of the control unit is the Start bus. 2. The converter according to claim 1, characterized in that the control unit is executed on the first and second registers, an inverter, a permanent storage device, n inputs of which, where n is the number of digits of the analog 9 of the digital converter, are the second inputs of the control unit, inputs from p + 1 to p + b are connected to the corresponding outputs of the second register, outputs from the first to the ninth are connected to the corresponding information inputs of the first register, outputs from the tenth Secondary entrance BU X Match signal Fifth output BOO Y, Control signal First output of control unit Y Sync pulse 1RG BU output Y BU output Y Sync pulse 1BRK Scan signal 1BRK and 2BRK The sixth exit BU Y Zero 2RG output Y output Y output Y th exit Y Sync pulse 2RG Shifting 2RG content Sync pulse recording 2BRK / Synchronization control  , .. D output signals 1BLE AND by the number of code bits. 23368 10 on the fifteenth, they are connected to the corresponding information inputs of the second register, the first control input of which is the third 5 input control unit, the second control input is connected to the output of the inverter, the input of which is combined with the control input of the second register and is the first input of the block 10 controls, first, second, third, fourth, fifth, sixth, seventh, eighth and ninth outputs of the control unit are respectively fifth, first, second, third, sixth, seventh, eighth, ninth and fourth inputs control unit. With ... vx 0 one of the BRK cleared When Y 1, the frequency changes