JPH06112825A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain high noise immunity and to improve the resolution at a high speed with high accuracy, by devising the A/D converter such that quantization at a voltage interval larger than a voltage interval equivalent to 1LSB is implemented to prevent an analog signal in the circuit from being too small. CONSTITUTION:A reference voltage at A/D conversion of high-order m-bits is given to a main reference voltage array 1 and its voltage interval Vsm is equivalent to 1LSB of a high-order A/D converter. A comparator 3 compares a reference voltage having the voltage interval from the voltage array 1 with an analog input voltage to generate a thermometer code. A high-order encoder 4 encodes the thermometer code and converts the code into a digital signal in high-order m-bit. The high-order m-bit A/D conversion is implemented corresponding to an amplitude of the analog input signal by combining the voltage array 1, the comparator 3 and the encoder 4. On the other hand, a vernier reference voltage array 2 whose voltage interval is Vsb (relation to the voltage interval Vsm is expressed in 2<n>Vsb=(2<n>-1)Vsm) is used for a reference voltage for low-order n-bit A/D conversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital converter (hereinafter AD) for converting an analog signal into a digital signal.
Regarding C), in detail, the main reference voltage train and the reference voltage train are compared with the vernier voltage train having a slightly different voltage interval and the input voltage is superimposed, and the vernier voltage train having the closest voltage value is compared. High-resolution AD that can be used for image processing, etc., based on the principle of detecting the position of the reference voltage train
Regarding C.

[0002]

2. Description of the Related Art A typical conventional serial-parallel ADC is shown in FIG.
Will be described with reference to. First, the high-order ADC 21 performs A / D conversion at a coarse voltage interval to obtain a high-order bit digital signal. Next, the digital signal of the higher-order bits is returned to an analog signal by a digital-analog converter 22 (hereinafter referred to as an internal DAC) provided inside, and the restored signal is subtracted from an analog input signal by a subtractor 23. Then, the subtraction result is amplified by the amplifier 24 as necessary, and the lower A
A / D conversion is performed by the DC 25 to obtain a digital signal of lower bits. Finally, the high-order bit and the low-order bit digital signals are added by the digital adder 26 to obtain the entire digital signal.

[0003]

DISCLOSURE OF THE INVENTION Conventional serial-parallel type ADC
Since an internal DAC, a high-precision subtractor and a high-precision amplifier are required, the settling time of the DAC and the response speed of the high-precision amplifier dominate the response speed of the entire ADC.
In addition, the accuracy causes a problem that the differential phase and differential gain deteriorate when used for video and TV applications when the connection between the upper conversion unit and the lower conversion unit is not smooth due to the variation in the offset of the subtractor and amplifier. Was there. Further, since the input signal is an analog signal, an internal DAC for converting the result of the higher ADC into an analog signal is necessary to take the difference from the result of the higher ADC.
C has a problem that glitches often occur due to switching of clock signals and the like, and when viewed as an image, the screen is flickering and is very difficult to see.

The output of the subtractor is 1 of the upper ADC of the upper conversion.
Since the size is equal to or smaller than LSB, it is common to amplify with an amplifier before inputting the lower ADC. The amplifier at this time must be accurate to within 1 LSB of the lower ADC. If the gain of the amplifier varies, there is a problem in that there is a step difference in linearity as in the case of offset. In addition, since the signal level of the process between the output of the subtractor and the input of the amplifier is less than 1 LSB of the higher ADC, there is a problem that digital noise is very weak. If a small amount of noise is superposed before the input of the amplifier, the noise is also amplified and the lower ADC
Will be converted by. The metastable state in the lower ADC frequently occurred. Since the ADC is a mixture of digital and analog, it is extremely difficult to completely block the interference of digital noise on the analog side. Ideally, the minimum amplitude of the analog signal should be as large as possible, but the conventional method has a problem that the minimum amplitude handled by the analog becomes smaller in proportion to a power of 2 as the number of bits increases.

Further, the serial-parallel type ADC requires two ADCs for upper conversion and lower conversion. For this reason, high-speed A /
It is not easy to realize a D converter, and processing such as trimming is required, and there is a problem in that it is effective. In recent years, it has been used for applications such as HDTV and ultrasonic diagnostic equipment.
There is an increasing demand for an ADC that operates at a clock frequency of about 30 MHz with a bit resolution. In particular, for generalization of HDTV, it is essential to supply a high-speed, high-resolution ADC at a low cost. In the field of measuring instruments,
A 12-bit ADC with a performance of 100 MHz or higher is required. However, at present, ADCs that meet such requirements are very expensive for industrial use, and there are few inexpensive ones for consumer use.

[0006]

In order to solve the problems as described above, the analog-digital converter of the present invention has a main reference voltage string having a voltage interval of Vsm and reference voltages of the main reference voltages. And a comparator for determining the upper m bits for comparing the levels of the analog input voltage and the voltage interval for determining the lower n bits are Vsb and Vsm, and 2 ⁿ Vsb = (2 ⁿ −1) Vsm A vernier reference voltage sequence provided so as to satisfy the conditions; an adder for adding an analog input signal to each reference voltage of the vernier reference voltage sequence; and a reference voltage for each of the main reference voltage sequences and each of the adders. The closest detection means for detecting the position of the vernier reference voltage train where the output is the closest, and the upper m-bit digital signal with respect to the analog input signal are obtained based on the output result of the comparator. The upper encoder, those provided with the lower encoder to obtain a digital signal of the lower n bits for the analog input signal based on the output result of the nearest detector.

[0007]

The main reference voltage train is used to provide a reference voltage for A / D conversion of the upper m bits. The voltage interval Vsm of this reference voltage corresponds to 1 LSB of the high-order ADC. The comparator compares each reference voltage of the voltage interval Vsm given from the main reference voltage string with the analog input voltage, and outputs a thermometer code (similar to the display of the thermometer and from the smaller reference voltage to the logic 1 state or Code with a single transition from the logic 0 state to the opposite logic state). The high-order encoder works to encode the thermometer code and convert it into a high-order m-bit digital signal. The above main reference voltage series, the comparator and the upper encoder are combined to function as an upper m-bit A / D conversion corresponding to the magnitude of the analog input signal. The vernier reference voltage sequence provided so that the voltage interval is Vsb and Vsm satisfies 2 ⁿ Vsb = (2 ⁿ −1) Vsm is the lower n
It is used as a reference voltage for A / D conversion of bits.

The adder adds the analog input signal to each reference voltage of the vernier reference voltage train, and operates so that each reference voltage of the vernier reference voltage train moves according to the magnitude of the analog input signal. The range selector selects a range of each reference voltage of the vernier reference voltage train and each reference voltage of the main reference voltage train to be compared, based on the conversion result of the higher-order ADC. The closest detection means operates to detect the reference voltage of each main reference voltage string selected by the range selector and the location of the output of the adder where the output of each adder is closest. The location of the output of the adder or the location of the vernier reference voltage sequence detected by the closest detection means corresponds to the value of the lower bit. The lower encoder operates to obtain a lower n-bit digital signal for the analog input signal based on the output result of the closest detection means. The digital adder sums the upper m-bit signal and the lower n-bit signal, and outputs the final (m + n) -bit analog-digital conversion result.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an analog-digital converter to which the present invention is applied will be described with reference to the drawings. First, the outline of the principle of the analog-digital converter of the present invention will be briefly described with reference to FIG. FIG. 2 is a diagram for explaining the basic concept of the principle of the present invention, and shows the values of the reference voltages of the main reference voltage train and the reference voltages of the vernier reference voltage train. The voltage of Vb0 in the vernier reference voltage train is equal to the analog input signal. Vm-1 to Vm9 are reference voltages of the main reference voltage train, and the voltage interval Vsm is 8 mV. Vb-1 to Vb9 are vernier reference voltages, and the voltage interval Vsb is 7 mV. Here, if the voltage of Vm0 is set to 3.000V and Vb0 is made equal to the input voltage of 3.005V, each reference voltage of the vernier reference voltage series has a position where the voltage is closest to each main reference voltage. It is Vb5.
“5” of Vb5 is 5 mV of input voltage 3.005V
Means 1LSB of a general all-parallel ADC using a reference voltage with a voltage interval of 8 mV is equivalent to 8 mV, and the voltage resolution is 8 mV. On the other hand, in the present invention, 8 m
By providing a vernier reference voltage with a voltage interval of 7 mV, which is smaller than V by 1 mV, and detecting the closest voltage, a voltage resolution of 1 mV is obtained.

FIG. 1 is an embodiment of the present invention and is a circuit block diagram for explaining the minimum required function.
In the figure, 1 is a main reference voltage train that generates reference voltages at equal intervals by resistance or capacitance, 2 is a vernier reference voltage that generates a voltage gap Vsb that is slightly smaller than the voltage interval of the main reference voltage train, and 3 is a main reference. A comparator 4 which compares each reference voltage of the voltage series with the analog input voltage and quantizes the input voltage at the voltage interval Vsm is an upper encoder which encodes the result of the comparator.

A combination of the main reference voltage train 1, the comparator 3 and the upper encoder 4 functions as a parallel type ADC quantized at the voltage interval Vsm. This is the upper ADC. Vs
m corresponds to 1 LSB of the upper ADC, and this upper 1 LSB
Further, n-bit quantization is performed by the method described below. Assuming that the number of bits of lower-order quantization is n [bit], the minimum required number of vernier divisions is 2 ⁿ . Here, the relationship between Vsb and Vsm is as follows. Vsb2 ⁿ = (2 ⁿ -1) Vsm ‥‥‥‥‥‥‥‥‥‥ (1) Here, it is important that Vsb is an integral multiple of the vernier voltage and Vsm is a multiple of Vsm that is one less than the integer.
is equal to the voltage of m. The upper ADC may be a general parallel type. The voltage interval of the reference voltages of different magnitudes connected to the respective comparators of the parallel ADC is Vsm. The output of the parallel ADC comparator outputs a thermometer code.

FIG. 3 shows an embodiment of the main reference voltage train and the comparator in the high-order ADC. In the figure, the same reference numerals as those in FIG. 1 or 2 indicate the same or corresponding ones, 9 indicates a comparator, and 10 indicates a gate of an exclusive OR. In FIG. 3, the gate of the exclusive OR of adjacent comparator outputs is
When it is 0, the logic "1" is set to be on only when the outputs of the adjacent comparators are different. The presence or absence of this exclusive OR is not essential to the present invention, but is provided in order to simplify the logic of the range selector described later and to reduce accidental miscodes. FIG. 4 shows an embodiment of the adder and the vernier reference voltage. The adder is a circuit that adds an analog input voltage to each vernier reference voltage with one reference voltage in the vernier reference voltage string as a reference. In the figure, Vb-4 to Vbx are outputs of the adder. Due to the virtual short circuit of the negative feedback operational amplifier 11, Vb0 becomes a voltage equal to the analog input voltage Va. The current value Ir of the constant current source is set so that the voltage generated across the resistor Rb becomes Vsb, and the current value Ir, the resistor Rb,
The following relationship is established between the voltage and the voltage Vsb. Ir = Vsb / Rb ‥‥‥‥‥‥‥‥‥‥‥ (2)

In FIG. 2, the input voltage Va of the input signal is between Vm0 and Vm1. The respective voltage values of the main reference voltage series are as follows. ::: Vm-1 = Vm0-1Vsm Vm0 = Vm0 1Vsm Vm1 = Vm0 + 1Vsm Vm2 = Vm0 + 2Vsm :::: Vmx = x at the main voltage, and at the Vmx == Vsm-the Vm0- is there.

The vernier reference voltage Vb0 is used as the input voltage Va.
And each value of the vernier voltage is as follows. ::: Vb-1 = Va-1Vsb Vb0 = Va Vb1 = Va + 1Vsb Vb2 = Va + 2Vsb Vb3 = Va + 3Vsb ::::: Vsx: = Vax.

The closest detection means 6 of FIG. 1 compares the output result of the adder with the voltage of the main reference voltage series, and the output voltage of the adder and the reference voltages of the main reference voltage series are closest to each other. However, the output terminal of the adder is detected. For example, in FIG. 2, Vm0 and Vb0 are compared, Vm1 and Vb are compared.
1 is compared with Vmx and Vbx.
In the drawing, since 7Vsm = 8Vsb, n = 3 is obtained from the equation (1), and the lower quantization level is 3 bits. That is, quantization can be performed with a voltage obtained by dividing Vsm into eight. Vb0 is between Vm0 and Vm1, and when the scale is 1 mV, the voltage is Vm0 to 5 mV. This scale is written for convenience of explanation, and actually there is no reference voltage at the intervals of this scale. Vmx and Vbx with the same terminal number
Comparing with each other, Vm5 and Vb5 have the closest voltage. From this result, the magnitude of the analog input signal is Vm0 + 5 [mV].
It can be seen that it is. In this way, Vsm can be quantized with a resolution that is further divided into eight. The resolution Vres is as follows. Vres = Vsm / ²ⁿ ‥‥‥‥‥‥‥‥‥‥ (3)

The lower encoder 7 shown in FIG.
The digital adder 8 is a circuit for encoding the output of the closest detection means to obtain a digital signal of the lower bit, and the digital adder 8 is a circuit for digitally adding the output of the upper encoder and the output of the lower encoder. With the above configuration, (m + n) -bit analog-digital conversion can be performed.

FIG. 5 shows another embodiment in which a range selector for selecting the range of the main reference voltage to be compared with the output of the adder is provided. The selector in this range selects the reference voltage range of the main reference voltage string to be compared with the output voltage of the adder according to the result of the high-order ADC. In the figure, the same reference numerals as those in FIG. 1 are the same or equivalent, and 12 is a range selector. By providing the range selector 12, it is not necessary to compare the entire range of the main reference voltage, so that the circuit can be simplified. Range selector 12 is the upper A
It is a switch for accurately transmitting a reference voltage in a predetermined range of the main reference voltage train in accordance with the result of DC to the input terminal of the window comparator included in the closest detection means 6 or the like. This switch can be easily realized by a CMOS transfer gate and a logic circuit. In the figure, the control signal of the range selector 12 is directly input from the comparator 3, but the output of the upper encoder 4 may be input.

FIG. 6 shows an embodiment using a window comparator as the closest detection means. In the drawings, the same reference numerals as those in FIG. 1 or 5 indicate the same or corresponding ones.
Reference numeral 3 is a window comparator, and 14 is a window width reference voltage. An example of the truth table of the range selector 12 of the range selector 12 is shown in FIG. 7 using the window width reference voltage 14 which is a predetermined window voltage of the window comparator 13. FIG. 7 shows the output range of the upper ADC and the reference range of the main reference voltage with respect to the analog input voltage. M1 to M26 are absolute terminal numbers of the main reference voltage. In this case, Vm-1 to Vm9 in the main reference voltage train shown in FIG. 3 are voltages according to the relative position that changes depending on the analog input. Since 11 vernier reference voltages are compared in this embodiment, 11 main reference voltage reference ranges are also selected.

On the other hand, the vernier reference voltage train has a voltage interval of Vsb determined by the equation (1), and the required number of vernier reference voltages is as follows. Nb = 2 ⁿ + K (4) Here, K is the number of window comparators that are turned on at the same time, and is an odd number. The locations of the odd numbered window comparators correspond to the values of the lower bits. When the value of K is larger than 1, the increase amount of Nb is K-1.
Therefore, the voltage range to be compared is (K-
1) / 2 up and down.

For example, when K = 3 and n = 1, the range of the main reference voltage train is Vm0 to Vm8, the range of the vernier reference voltage train is Vb0 to Vb8, and nine reference voltages are compared. . When K = 3 and n = 3, the range of the main reference voltage train is Vm-1 to Vm, 9 and the range of the vernier reference voltage train is Vb-1 to Vb9, and 11 reference voltages are compared. To do. Similarly, when K = 5 and n = 3, the range of the main reference voltage train is from Vm-2 to Vm1.
0, the range of the vernier reference voltage train is Vb-2 to Vb10
And 13 reference voltages are compared with each other. The window voltage width Vw of the window comparator is expressed by the equation (5). (K-1) (Vm-Vs) ≤ Vw <K (Vm-Vs) ... (5)

The value of K is arbitrary as long as it is a positive odd number.
Actually, it is better that the window width of the window comparator is as large as the voltage width of 1 LSB of the ADC for obtaining the upper bits, so when n is the number of lower bits, the value of K is K = 2 ⁿ +1. ‥‥‥‥‥‥‥‥‥‥‥ (6) or K = 2 ⁿ -1 ‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (7) It is realistic to set it near. The smaller the value of K, the smaller the circuit scale, but the smaller the window width.

In this embodiment, the case where n = 3 and K = 3 will be described. FIG. 8 shows the adder, the vernier reference voltage train, and the window comparator of this embodiment. In FIG. 8, the same symbols as those in FIG. 4 or FIG. 6 indicate the same or corresponding ones, and Rbb and Rwh indicate resistance. The adder 5 is the same as that shown in FIG. 4, but a resistor Rwh for supplying a window voltage is added. Rb in FIG. 4 is represented as follows in FIG. Rb = Rbb + 2Rwh (8) The relationship between the voltage interval Vbs of the vernier reference voltage train, Rb, and Ir is the same as the relationship shown in equation (2). Vb0, Vb
, ..., Vbx are respective vernier reference voltages.
The window voltage Vw is given as follows. Vw = 2Rwh Ir ‥‥‥‥‥‥‥‥‥‥‥‥ (9)

The central voltage of the window voltage Vw is set to the vernier voltages Vb0, Vb1, ..., Vbx. The upper limit voltage Vbxu and the lower limit voltage Vbxd of the window voltage in each window comparator 13 are as follows when the vernier voltage is Vbx. Vbxu = Vbx + Vw / 2 ‥‥‥‥‥‥‥‥‥ (10) Vbxd = Vbx-Vw / 2 ‥‥‥‥‥‥‥‥‥‥‥ (11)

With the configuration shown in FIG. 8, the vernier voltage and the window voltage can be accurately supplied to the window comparator 13. Range selector 1
2 selects the range of the main reference voltage string Vmx according to the result of the high-order ADC. The selection range is the same number of main reference voltages as the number Nb of vernier reference voltages. Window comparator 1
The comparison in 3 is to compare Vmx and Vbx having the same suffix x.

A specific example will be described below. FIG. 9 shows the input condition. For example, in FIG.
m0 is defined as 3V, and the analog input terminal is 3.
If 005V is between Vm0 and Vm1, EX
-Only the S0 terminal of the output of the OR gate 10 is in the logic "1" state. This output is input to the range selector 12. This is because the input voltage at the bottom of Fig. 7 is 3.00.
It is in the state shown in the 0V row. The range selector 12 is shown in FIG.
As shown in, the voltage range of the main reference voltage string of M1 to M11 is selected. The range selector 12 outputs the voltage of the main reference voltage string at the absolute positions M1 to M11 in FIG. 3, and this voltage is the input Vm of the window comparator 13 shown in FIG.
-1 to Vm10. Vernier reference voltage is
The adder 5 of FIG. 8 generates a vernier reference voltage at a voltage interval of Vsb while maintaining Vb0 at a voltage equal to that of the analog input signal.

FIG. 10 shows the value of each reference voltage Vmx of the main reference voltage series (the output voltage of the range selector), the value of each reference voltage Vbx of the vernier reference voltage, and the output of the window comparator 13 in FIG. Indicates the state of. The output of the window comparator 13 is W4, W4,
It is in the state of logic "1" at W6. This is the window voltage 1 of these three window comparators 13.
It is shown that the output voltage of the range selector 12 is within the range of 4. The reason why the exits of the three window comparators 13 are logic "1" is that K = 3 and the window width is three times the resolution. The center position of the window comparator 13 that outputs a logic "1" means the result of AD conversion of the lower n bits.
In this case, the position is W5.

The output of each window comparator 13 is input to the lower encoder 7. FIG. 11 shows a truth table of the lower-order encoder 7. Since the outputs of the window comparator 13 are logic "1" for W4, W5, and W6, the output of the lower-order encoder 7 is set to (0101) 2. This is because the result of lower A / D conversion is 5 LSB
Means that. The result of the ADC of the lower 3 bits and the result of the ADC of the upper m bits are summed by the digital adder 8 to obtain the result of the ADC of (m + 3) bits. As described above, the upper ADC finds that the level of the input signal is within the range of 3.000 to 3.008 V, and the lower 3 bits of A / D
By conversion, 0.005V voltage can be obtained with 1mV resolution, and the final result is 3.005V input voltage.
You can know that.

In this embodiment, since K = 3, the window voltage is 3 mV, and the minimum voltage handled in the circuit is 3 mV, but a resolution of 1 mV can be obtained.
For example, when the window voltage coefficient K = 7, a resolution of 1 mV can be obtained at a voltage interval of 7 mV. As shown in this embodiment, in the analog-digital converter of the present invention, the minimum voltage handled as the analog reference voltage can be increased by increasing the value of K. In the conventional method,
When the number of bits increases by 1, the minimum voltage handled in the circuit becomes 1/2. In the conventional method shown in FIG. 12, the magnitude of the output of the subtractor can be a value obtained by dividing the input full-scale voltage Vf by the total number of bits (m + n).

For example, if the input voltage is 3.001V,
2. The voltage resolution of the higher ADC is 8 mV and 3.000 to 3.
The output of the subtractor is 1 mV, assuming it is between the reference voltages of 008V. Equation (12) shows the minimum voltage Vmin1 handled in the circuit of the conventional analog-digital converter. Vmin1 = Vf / 2 ^{(m + n)} (12) On the other hand, in the present invention, the minimum voltage Vmin2 handled in the circuit is
It is expressed as in Expression (13). Vmin2 = K Vsb = K (2 ^(n-1) Vf / 2 ^{(m + n)} ) ‥‥‥‥‥‥‥‥ (13)

As described above, by increasing K by the amount of decrease in the minimum voltage due to the increase in the number of lower bits, the minimum voltage handled in the circuit can be prevented from becoming too small. Various well-known configurations can be used as the configuration of each unit of the above-described embodiment without departing from the spirit of the invention. For example, as the closest detection means, a subtracter that takes the difference between the output voltage of the range selector and the output voltage of the adder, an absolute value circuit that converts the subtraction result into an absolute value, and the output of the absolute value is the smallest. A method of constructing a minimum detection circuit for detecting the vernier position is possible. Alternatively, as the closest detection means, a subtracter that takes the difference between the output voltage of the range selector and the output voltage of the adder, and a zero-cross detection circuit that detects the vernier position closest to the point where the output of the subtractor crosses zero It is also possible to use

As another adder, an adder for adding the analog input signal and each vernier reference voltage is prepared by the number of vernier reference voltages, and the respective adders are added to generate a vernier voltage in which the analog input voltage is superposed. It is also possible to provide an adder / subtractor that generates window voltages above and below the window comparator above and below each vernier voltage.

[0032]

As can be understood from the above description, the analog-digital converter of the present invention can be quantized by a voltage interval larger than the voltage interval of 1LSB, and the analog signal in the circuit does not become too small. Since it has extremely high noise immunity and does not require a high-precision internal DAC or amplifier, it has high speed and high accuracy, and its resolution can be improved compared to the conventional ADC, and it can be widely used in applications such as HDTV. Above Use range and value are high.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a voltage distribution diagram of a main reference voltage train and a vernier reference voltage train for explaining the operation principle.

FIG. 3 is a circuit diagram of an analog-digital conversion unit for upper bits.

FIG. 4 is a circuit diagram of an adder that adds a vernier voltage and an input voltage.

FIG. 5 is a circuit block diagram showing another embodiment provided with a range selector.

FIG. 6 is a circuit block diagram in which a window comparator is used as the closest detection means.

FIG. 7 is a table diagram showing a relationship between an analog input voltage, an output of an analog-to-digital converter of upper bits, and a selection range of a main reference voltage string.

FIG. 8 is a circuit diagram of an adder and a window comparator when a window comparator is used.

FIG. 9 is a table showing input conditions.

FIG. 10 is a table diagram showing an output state of a window comparator.

FIG. 11 is a conversion table diagram of a lower encoder.

FIG. 12 is a circuit block diagram of a conventional serial-parallel type analog-digital converter.

[Explanation of sign]

 1 main reference voltage sequence 2 vernier reference voltage sequence 3 comparator 4 upper encoder 5 adder 6 closest detection means 7 lower encoder 8 digital adder

Claims (4)

[Claims] 1. An analog-to-digital converter for converting an analog signal into a digital signal representing its amplitude with upper m bits + lower n bits (m and n are integers),
The main reference voltage train having a voltage interval of Vsm, a comparator for determining the upper m bits for comparing the level of the analog input voltage with each reference voltage of the main reference voltage, and the voltage interval for determining the lower n bits are provided. the relationship between Vsm with ^{Vsb, 2 n Vsb = (2} n -1) and the vernier reference voltage column provided so as to satisfy the Vsm, addition for adding the analog input signal to each of the reference voltage of the vernier reference voltage columns Based on the output result of the comparator, the closest detection means for detecting the position of the vernier reference voltage train where the reference voltage of each of the main reference voltage trains and the output of each of the adders are closest. And an encoder for obtaining a digital signal of upper m bits for the analog input signal, and a lower n bits of data for the analog input signal based on an output result of the closest detection means. Analog-to-digital converter, characterized by comprising a lower encoder to obtain a barrel signals. 2. A range for selecting a range of the reference voltage series necessary for comparing the output of each of the adders and the reference voltage of each of the main reference voltage examples based on the output result of the comparator. The analog-digital converter according to claim 1, wherein a selector is provided to limit a range of the reference voltage sequence to be compared with the vernier reference voltage sequence. 3. The closest detection means is a window voltage width Vw.
(K-1) (Vm-Vs) ≤Vw <k (Vsm-Vs
b) (K is a window voltage coefficient and a positive odd number), the output of the range selector is connected to the input of the window, and Vbx is the vernier reference voltage, the upper limit voltage of the window voltage. Vwu, lower limit voltage Vwl
Is Vwu = Vbx + Vw / 2 Vwl = Vbx−Vw / 2, and Vmu and Vml are connected to the window terminals of the window comparators, respectively, and k
2. The analog-to-digital conversion according to claim 1, wherein the lower bit digital signal corresponding to the location of the (k + 1) / 2nd window comparator located in the center of the turned-on window comparators is output. vessel. 4. The adder and the vernier reference voltage train are composed of a plurality of divided resistors, an amplifier and a low current source, the resistors being arranged in series in a negative feedback loop of the amplifier, and the output of the amplifier. A constant current source is connected in series with the resistor, the current of the constant current source and the resistance value are set so that Vsb is generated at both ends of the resistor, and an analog input signal is input to the non-inverting terminal of the amplifier. As a result, the analog input voltage and the voltage of the resistance terminal connected to the inverting terminal of the amplifier become equal due to the virtual short circuit of the amplifier, and vernier voltages at equal voltage intervals based on the analog input voltage are generated. The analog-digital converter according to claim 1.