SU1226477A1 - Selector channel - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in a computer for the exchange of information between RAM and external devices. The aim of the invention is to increase channel capacity. The goal is achieved by the fact that the readiness register of external devices, coincidence register, node, are entered into the selector channel containing interfacing units with random-access memory, external devices and central processor, channel firmware control unit, exchange register and control word formation node. priority, register of initiated exchanges, register of initial states, register of masses and register of readiness of the program. 4 hp f-ly, 8 ill. i t to O) 419 -Nj sj

Description

one

The invention relates to the field of computing and can be used in digital computers (DVR) for the exchange of information between RAM and external devices.

The aim of the invention is to increase the capacity of the selector channel.

FIG. 1 shows a block diagram of the device; FIG. 2-7 are functional diagrams of an interface unit with a random access memory, a interface unit with a central processor, a interface unit with external devices, a priority node, a channel control unit and a control word generating unit; FIG. 8 is a flowchart of a channel control block.

The selector channel (Fig. 1) contains the exchange register 1, the interfacing unit 2 with the operational memory, the control word generation unit 3, the channel microprogram control unit 4, the central processor interfacing unit 5, the source status register 6, the register 7 initiated exchanges, register 8 of masks, register 9 of program availability, register 10 of readiness of external devices, priority node P, register 12 of readiness of readiness, block 13 for interfacing with external devices. The device provides information exchange with external devices on buses 14 and 15 of the output and communication input with external devices. The information comes from (c) external devices through the exchange register 1 and further to (from) the operative memory (not shown) from the output of block 2 under the control of signals from block 4, which uses control words recorded in node 3, Service signals of readiness for the exchange of external devices (WU), received in the device bus 15, are received through the block 13 to the input of the register 10.

The selector channel provides information exchange with a set of external devices (sources and consumers of information in accordance with the priority of subchannels. One or more external devices can be connected to each of the subchannels via block 13 and buses 14 and 15).

The selector channel has direct access to the memory (in Fig. 1, not yet |

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Zano) through the block 2 ratikny memory

ten

|; 5

20

25

thirty

35

XiO

45

SO

interface with one- The connection with the processor (not shown in Fig. 1) is carried out with the help of operations with addressable registers and features through the processor interface 5.

The operative memory interface 2 contains (FIG. 2) the OR elements 17 and 18 of the first and second groups and the address coder 16 for generating the address of the operative memory cell by register value 12 and by the signals of block 4. The third input of the elements OR 18 is sent to the second and first inputs of which are sent the bits of the address code from block 4 and the output of node 3. Signals from the outputs of elements OR 18 go to the address memory register (not shown). The elements OR 17 receive information from two directions: from register 1 and node 3 .. elements OR 17 are connected to the numerical memory register. The information from the numerical memory register goes to register 1 and node 3. To provide a temporary memory diagram, block 4 receives a readiness signal from the memory (not shown).

The interface unit 5 with the central processor contains (FIG. 3) the address decoder 19, the AND-20-26 elements of the central and seventh groups, and the elements of the OR-27 group. Elements 20 receive a command for the channel from a processor command register (not shown). The other inputs of the elements And 20 receives the channel address from the address part of the command (there can be several selector channels in the digital computer). During operations with addressable registers, the register number from the address part of the command goes to the decoder address 19 of the register, from the output of which the permission signals together with the bits of the characters (read, write) from the processor go to elements 21-23 (read from the register) and elements And 24-26 (write to the register). The second inputs of the AND 21-23 elements are received respectively by the values of the registers 6-9, which from the output of the AND 21-23 elements through the OR27 elements go to the buffer registers of the processor (not shown). Back from the iJiepHbix registers of the processor, the value of the addressable register goes to the second inputs of the AND 2A-26 elements and then to the registers 6-9, respectively.

Block 13 interface with external devices contains (Fig. 4) groups of amplifiers-transmitters 28 and 29, groups of amplifiers-receivers 30 and 31, elements AND 32-35 of the first to fourth groups, elements OR 36 and 37 of the group and element AND 38. Among the service signals received from VU there are signals of readiness to exchange a portion of information. These signals are captured on the external device register 10. Information from the exchange register 1 is passed through the elements of AND 32. Service signals from 4 are sent to amplifiers through the elements of AND 33. Information signals are sent to the exchange register 1 through the elements of AND 34 and the elements of OR 36; the service signals arrive at block 4 through the elements AND 35 m of the elements OR 37. The second inputs of the elements AND 32-35 receive the permission signals from the register 12 of readiness, ensuring selection of the subchannels. Among the service signals from block 4, a signal is received for polling the initial states at the input of the And 38 element, to another input of which the register value of the six initial states is received. The output signal for WU from the And 38 element, along with other service signals, is fed to the first inputs of the And elements 33 and then transmitted to the WU.

The priority node 11 contains (FIG. 5) elements AND 39 of the first group (by the number of subchannels) and elements 40 of the second group. The input of each element And 39 receives signals from the corresponding bits of the register 8 masks, register 9 program readiness and register 10 readiness of external devices. Priority node 11, under the control of the signal from block 4, selects the most senior subchannel from among those that have set their readiness and writes the number of this subchannel in the position code to the register 12 of readiness.

The channel control unit 4 can be implemented on a firmware basis, the principle and contains (FIG. 6) a permanent memory 41, a microcommand address decoder 42, a microcommand address counter 43 and a microcommand address multiplexer 44.

ten

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Unit 4 operates in accordance with the program (Fig. 8), recorded in memory 41.

The control word processing unit 3 includes the address-command register 45 (the first control word-CSS), which in turn includes two fields: the address-command field for the VU and the attribute field for the channel, and the second register control word (US2), which runs on a 46 word counter and 47 current address counter 47, as well as element 47, on one input of which the value of counter 46 goes, and on the other input - polling pulses from block 4. At the same time As the next word is received (received), + is added to counter 47 and -1 is subtracted. tchika 46. If the counter value is equal to zero signal 46 from its output to the input element 47 and pass the resolving pulse counter 46 in the polling unit 4.

Reading the addressable register 9 of program availability, as well as other addressable registers, can be performed from the processor through block 5 with the processor without interrupting the operation of the channel using the instruction Read addressable register. In this case, the instruction specifies the number of the addressed register 6.8 or 9 and the sign Read from this register. The register number is 6.8 or 9 35 and is fed to the decoder 19, from the output of which the enabling signal is fed to the inputs of the elements 21-21, and the sign. Reading - to other inputs of these elements. Only those elements of AND 21-23 will be open, at the inputs of which there is a rasreshayuyushchy signal from the outputs of the register address decoder 19.

The selector channel works as follows.

25

thirty

40

,

The selector channel provides

exchange with contributors (WUs) over a group of subchannels in exclusive mode, and it is possible

interrupt the exchange on one subchannel exchange on a subchannel having a higher priority.

Subchannel swapping is done by assorted words. At the same time, the first word of the array is given a command word with a different characteristic for a VU (1and address for a VU). The address- command is part of the management of the

The WORD for the channel (part of CSS 1) is fixed on node 3.

To fix the subchannels with which the exchange has already begun (the command issued by the address) S uses the register of 7 initiated exchanges where the subchannels are fixed by the position code.

The selector channel can also reset the WU to its original state by issuing an appropriate overhead signal there. The information for this vyyachi is the contents of the register 6 of the initial states, where in the positional code there are numbers of subchannels (one or several) that must be set in the initial state.

The channel operation is performed in accordance with the algorithm of FIG. 7. After forming an array of control words (US) and US2, the contents are written to the program readiness register 9, the mask register 8, and the register of 6 initial states. The recording is made on the processor side through block 5 without interrupting the operation of the channel using the instruction Write to the addressed register. At the same time, the instruction-address-instruction specifies the number of the addressable register (6.8 or 9) and the attribute Write to this register. The register number is fed to the decryptor 19, which generates a write enable signal for the Record sign - to the inputs of AND 24-26 elements. The recording will occur only in the addressed register of the channel 6,8 and 9, the number of which is indicated in the instruction and is decoded by the decoder 19.

On register 10, the readiness of the VU is recorded, which come from the VU with special signals comprising weak signals via the block 13 of the interface with external devices, and in the latter through the amplifiers-receivers 3.

Next, from the processor side, the selector channel is started using the channel Start instruction. The operation code in this case arrives at the elements AND 20, to the other inputs of which the signal of the address of this channel is given (since there may be several channels). If in the instruction of the decree the code (address) of this channel, then the operation code of the start of the channel goes to block 4 and in the latter the set

0

0

five

five

initial microcommand of exchange operation. Next, the channel operates autonomously under the action of micro-operations from block 4. Only the processor can stop the channel by issuing a channel stop instruction.

In the course of channel operation, block 4 polls the register of 6 initial states by signal to the input of element 38, to another input of which register 6 arrives. The output signal for the CU from element 38 is received along with other 1 and service signals from the first The 5 inputs of a group of elements And 33 and onwards are transmitted to the slave through amplifiers-transmitters 29.

Next, control block 4 sends a signal to priority node 11, which determines the most senior subchannel from among those ready for exchange. The number of the selected subchannel is transmitted to the readiness register 12, where it is kept for the entire duration of the exchange with the selected subchannel.

According to the selected subchannel number, the address of the memory cell (RAM) is formed, where the exchange order (US1 and US2) for the given (selected) subchannel is stored. The address is formed in block 2 using the address encoder 16, the inputs of which receive signals from block 4 of register 12 of readiness. The generated address through the elements OR 18 enters the address memory register. At this address, the values of US1 and US2 are written to node 3.

Under the influence of signals from block 4, the part of the US 1 (address-command) is transmitted to the exchange register 1 and then through block 13 to the corresponding slave (connected to this subchannel). The address of the command address in the slave occurs only at the beginning of the exchange for this subchannel.

When the address-command in the VU is entered, unit 4 enters 1 into the corresponding register bit 7 (the connection in FIG. Is not shown). When exchanging the next word in block 4, the state of the corresponding register register 7 of the exchanges started is analyzed, the search request is thus followed by the subsequent address-command for this subchannel.

Among the signs accepted in the composition of US1, contains the sign on 0

five

five

0

7

Board of Exchange Reception-In. Signs from the register 45 are received in block 4, where, depending on the direction of the exchange, a branch of the microprogram is produced: the word reception and VU branch and the word output branch in the VU.

When a word is received, it comes from the control unit through block 13 and then through elements AND 34 and elements OR 36 to the exchange register 1. This word is written to the RAM via the elements OR 17 on the numeric OP register.

The value of the write address in the OP comes from the counter 47 of the current address. The address passes the elements OR 18. The sign Record is also transmitted through the elements OR 18 from the half-sign of the register 45.

After recording in the OP, received from the word, the counter 47 of the current address and the counter of 46 words are modified.

When issuing a word to the control unit, it is read from the control unit to the exchange register 1 at the address recorded on the counter 47. Address and the sign Read is sent to the control unit through the elements OR 18 From the exchange register 1, the information word. Both 32 and transmit amplifiers 28. At the same time, the second inputs of the And 32 elements receive switching signals from register 12 of readiness coincidences providing switching of subchannels. Next, as in the case of word reception, counters 46 and 47 are modified.

After the end of the word exchange (reception or issue), an analysis of the presence of the sign of the exchange interruption on this subchannel takes place. This feature comes from the gender of the characteristics of the register 45 in block 4, where the analysis takes place. If there is a sign, then from block 4, the presence of older subchannels than the selected one and ready for exchange is analyzed on priority node 11. If there is an older subchannel, the signal from block 4 to the address encoder 16 is transferred to the operative memory, the address of the standard cell dp. Of the previously selected subchannel and the Record flag via the elements OR 18.

At this address, the contents of the control words (current

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value) by applying a signal from block 4 to the control inputs of US1 register 45 and counters 46 and 47. Next, return to the beginning of work, but with a higher subchannel. If there is no older channel or there was no sign of interruption of the exchange for this subchannel, an analysis of the number of words received

0 (issued) for this subchannel.

If the received (issued) number of words is equal to that specified in node 3, the final value is written to the standard memory cell.

) 5 control words in the address formed in accordance with the described case when a higher subchannel was detected. If the word is not the last, then, depending on the prize 2Q of Acceptance or Extradition, a transition occurs to the subroutines of receiving or issuing the next word, respectively.

After packing the final value of the control words in node 3, an enrichment (set in O) of the corresponding bit in register 9 of the program readiness and in register 7 of the initiated exchanges (connection of the installation in O is not shown in Fig. 1) occurs. If by this time the instruction to stop the channel has not come, the return to the beginning of the work of the channel program (organization of the exchange with other subchannels) occurs.

35 If the instruction Stop the channel for this selector channel arrives, the execution of the exchange operation is stopped and block 4 is stopped.

Thus, the proposed selector channel provides almost complete autonomy of the channel, which independently conducts the exchange on all ordered subchannels and in

 according to the availability of external devices. There is a combination in time of the actual exchanges with the program control on the part of the processor by receiving and issuing information of the nation.

Claims (5)

Invention Formula I. A selector channel containing 55 memory interfacing unit, the information and address output of which is the output of communication with the operational memory of the device; thirty interfacing with external devices For the first time, the information inputs and output are costly, respectively, the input and output of communication with external devices of the device, and the control input and output are connected respectively to the first output of the microoperations and the input condition of the microprogram control channel, the second input the conditions of which are connected to the output of the command of the interface unit with the central processor, the information input and output of which are respectively, the input and output of communication with the central processor of the device, the exchange register and the node of the formation of control words, the first information outputs of which are connected respectively to the first and second information inputs of the RAM interface, the control inputs to the second and third micro-operations of the microprocess control channel, the fourth output of the micro-operations, connected to the control input of the interface unit with the RAM, the third input of the conditions to the first information output of the control word command node, the first information input of the register exchange, the information input of the right-word shaping node and the fourth input of the conditions of the microprogram channel control block form the information input of the connection with the device’s RAM, which differs from the fact that, in order to increase the throughput of the selector channel, an external device readiness register was entered into it, readiness match register, priority node, register of initiated exchanges, initial state register, mask register and program readiness register, with the information I / O of the register and the output states, the mask register and the program readiness register are connected respectively to the first, second and third information inputs / outputs of the interface unit with the central processor, and their information outputs are connected respectively with the information input of the register of initiated exchanges and with the first and second information inputs of the priority node the third information input and output of the connected five with the output of the readiness register of external devices and the input of the register of readiness, the output of which is connected to the address input of the interface with memory, the control input of the register of initiated exchanges and the address input of the interface unit with external devices, the output of readiness connected to the input of the register of readiness of external devices, the second information input and output, respectively, with the second information output and the input of the exchange register, and the gate input - with the output of the initial state register, the output of the register of initiated exchanges is connected to the fifth input of the conditions of the microprogrammed channel control unit , the fifth output of micro-operations of which is connected to the control input of the priority node, the third information input of the exchange register is connected to the third information output of the formation node 5 control words. 2. A selector channel according to claim I, characterized in that the interface with the operative memory contains two groups of OR elements, the outputs of which form the information and address output of the block, and an address helper, the first inputs of the OR elements first and The second group is connected to the second information input of the block, and the second inputs correspond respectively to the first information and control inputs of the block, the first and second inputs of the address coder are connected respectively to the control and address inputs of the block, and output 0 to the third inputs of the OR elements Torah group. 3. A selector channel according to claim 1, characterized in that the interface unit with the central processor contains seven groups of AND elements, a group of OR elements and an address decoder, the outputs of the AND elements of the first group form the command output of the block, the outputs of the AND elements 0 of the second, third and fourth groups are connected respectively to the first, second and third inputs of the elements. OR groups, the outputs of which form the information output unit, the first 5 inputs of the elements of the first and seventh groups, the second inputs of the elements of the first, fifth, sixth and seventh groups and the input of the address decoder expanding the information input of the block, the second inputs of the elements of the second, third and fourth groups and the outputs of the elements of the fifth, sixth and seventh groups form the first, second and third information inputs-outputs of the block, the third inputs of the second and seventh groups are connected to the group outputs of the address decoder. 4. The selector channel according to claim 1., characterized in that the interface unit with external devices contains four groups of elements AND, two groups of elements OR, element AND, two groups of amplifier-receivers and two groups of amplifiers-transmitters, with outputs of elements AND The first and second groups are connected via amplifiers-transmitters of the first and second groups to the first information output of the block, the first inputs of the elements of the third and fourth groups are connected via the receiving amplifiers of the first and second groups to the first information input of the block, and the outputs - respectively, with groups of inputs of the elements OR of the first and second groups, the outputs of which are respectively the second information and control outputs of the block, the outputs of the amplifier-receivers of the second the groups form the unit ready output, the first inputs of the elements AND of the first group are the second information input of the block, the first inputs elements of the second group are connected to the control input 1 of the block and the output of the element i, the first input of which is connected to the control input of the block, and the second input is connected to the gate input of the block, the second inputs of the elements of the first and fourth groups form the address input of the block. 5. The selector channel according to claim 1, characterized in that the control word command node contains the address-command register, the word counter, the current address counter, and the AND element, the information inputs of the address-command register, the word counter and the current address counter are connected to the information input of the node, and the groups of outputs form the second information output of the node, the output of the address-command register is the first information output of the node, the output of the word counter is connected to the first input of the element I, the second input and output of which and the control inputs of the address-command register, the word counter and the current address counter form the control input of the node. izep R G. Tj f ffSC Tt FIG. to k5Ki9 -4-4--4-btp W Izs gv but ffl usjs-d KatnL Hpet Chee NVE Zatp 4G  XOHIHf V 11 .-. fipKmjM aeizna, “Zh p. i. pthssora "Otguft /,,;, Cm 5 ffm / z R thni ;  0m 8 Jll one eleven n3 oit and .r I one . r r t j. From 5 fmS  Oto ; g7 / 4J From .r I From 5 fmS 5.2 dr-com Signs dm VV 5 47 H tn From 5lM FIG. one Started Record Pr g / 7, pr :. lawsuit, Pr MS MC processor w / epsj 8l. five MHcmfH / cct on nj / cn i anajja J3 processor issuing Sample from dp insr. on Rg O at address / PS mustache Ana / shz HafifldS / efn,} sharingI Pzidacha Pro8 VU I eat izvuna t Record RGO TO) noadpecij P h s C Pz analysis Her / t R choice lx (by Pz gp, re, Re Bpr 7iПкпГ ° 1Г к с Janucb YL t Pr cr L A sample of us sgpand. cells OP US-1, K-. on Vegas AT-6 PeS Issuance of Reg 8 8, U (8y (7ta AK) Sent} PS BUT Modi (1 Ika14t addresses and Sc. Slod on the RS CM W-f from the sign of the prera - 6aeMOcm j exchange for the Pr CSS l / fw / wj cinapuiew Ш through VPr i cmb fjO / WCu PsW} Sc.frisfie. /. OP AnoAiz f in words not Pr  ffpifeti (. l onucb WGX § on t ; ydresi shA {final 13th value} I Cancellation de PsfTl, Rgno Editor T, Kugrpepeva Order 2135/49 Compiled by V. Ver Tehrets V.Kzdar Circulation 67 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company Ana (from stop us npoi eccopa pet there is Compiled by V. Vertlib Tehrets V.Kzdar Proofreader A. Ferenc Subscription Tie, Uzhgorod, st. Project, 4