SU1193682A1 - Interprocessor communication device - Google Patents

Abstract

A DEVICE FOR COMMUNICATION OF PROCESSORS, containing m memory blocks, m adapters, a synchronization unit, the first output of which is connected to the synchronization inputs of adapters, the first information input-output of the i-ro adapter (, t) is connected to the input-output of the i-ro memory block ,. buffer codes of the control code, where n is the number of connected processors, the input of the j-th buffer register (jr, n) of the control code is connected to a single output of the I / O channel of the j-ro processor, characterized in that, in order to increase performance processing information for exchange of information via shared memory blocks, a status register and 11 control output units are entered into it, the j-ro output of the buffer register is connected to the JM control code inputs of all adapters, the j-ro input of the control output unit is connected to the control output j-ro processor's I / O channel, () the sync block output and (j + l) -th information output of all adapters are connected to the j-ro input channel input channel of the j-ro processor, busy sign output and transmit i output -ro -adapter connected to the corresponding inputs of the status register, the output of which is connected to the information inputs. I / O channels of all processors, i-e memory capture outputs, freeing memory, signs of transmitting the j-ro signal output unit up. The connections are connected to the J-M inputs of the same i-ro adapter, each adapter contains from the first to the sixth OR elements, the AND, i element. counter, one-shot, trigger prize | (On busy, trigger to send, n capture triggers, n switches, the first inputs / outputs of which are combined and are the first information input-output of the adapter, the second inputs-outputs of the switches: tators are (j + l) - MH information (; adapter input inputs-outputs of the adapter with and connected to information inputs) dam-outputs of the input-output channels of the j-ro processor, respectively, input 00 1C of the control of the j-ro switch is connected to the output of the J-TO trigger capture je of the control code adapter connected to the inputs of the first element OR, the output to torogo connected to the information entry counter whose clock input is connected to the output of AND gate, first and second inputs connected to the input of a synchronization counter and yield, respectively, j-e inputs capture memory adapter connected to respective inputs of the installation

Description

jx of capture triggers and to the inputs of the second OR element, the output of which is connected to the first input of the fifth OR element, the output of which is connected to the occupancy sign trigger trigger input, the output of which is the output of the adapter occupancy sign, the adapter memory release inputs are connected to the reset inputs of the corresponding jx capture triggers and to the inputs of the third OR element, the output of which is connected to the first input of the sixth OR element and to the input of the trigger sign installation of the transmission feature, the output of which is the output of the sign adapter, the counter output, through a one-shot is connected to the second input of the sixth OR element, the output of which is connected to the reset input of the busy indication trigger, je inputs of the adapter’s transfer sign are connected to the inputs of the fourth IZHI output of the transfer indication trigger, to the second input of the fifth element OR and the record entry counter.

The invention relates to computing and can be used in the construction of multiprocess computers and multi-machine computing complexes. The purpose of the invention is to increase the productivity of information processing by exchanging information through shared memory blocks. FIG. 1 shows a functional diagram of the device for communication of the processors as a part of the computing system; in fig. 2 and 3-unit synchronization and timing of its work; in fig. 4 — memory block; in fig. An example of implementation of a control signal output unit. A device for communication of processors (Fig. 1) contains n processors 1 with input-output channels 2, m memory blocks 3, m adapters 4, synchronization block 5, state register 6, n buffer control code registers 7, blocks 8 of the control signal output, each adapter 4 including the first to the fifth elements OR 9-13, the trigger 14 of the transmission feature, the element AND 15, the counter 16, the one-shot 17, the sixth element OR 18, trigger 19 trait sign, n capture triggers 20, n switches 21. The main function The main element of the synchronization unit 5 is a ring counter j built on the shift register 22, the output of which is connected to the input containing n (by the number of processors 1 in the system) of bits to each of which the driver 23 is connected. of the bits of the shift register 22, when the power is turned on, a logical unit is entered, and in the remaining bits, a logical zero. The cyclic shift of information in the register 22 is carried out by pulses of the clock generator 24, which ensures that a sequence of clock signals, the distribution of which in time is illustrated in FIG. 3 (for example). Block 3i. the memory (, t) is connected to input / output channels 2 j (, n) using switches 21 j, each of which includes a set of bus drivers 25, and block 3; contains the number of bits R of the information word memory elements, address collector 27, consisting of address register 28, address comparison and trigger block 29, 30, word address register 31, first to third elements 32-34 ,. the OR element 35, the delay element 36, the fourth element AND 37. The control output unit 8 of FIG. 5) contains a matching unit 38 (on bus drivers), address selector 39, element 40, register 41, delay element 42. drivers: 43 | -43 (pulses. The device works as follows. In the system, simultaneously implements (according to the number of processors of computational processes, associated either with the collection and processing of measurement information, or with the solution of a problem presented in the form of a serial-parallel algorithm. For example, in an information-measuring system, one of the processors can , the admission control of technological or electrophysiological signals, as well as the formation of their arrays, another processor performs the primary processing of the data arrays previously formed by the first process (the allocation of informational signs, the reassembly of data with reference to the base time), and the third processor is executed static processing of recompiled new data arrays, computation and output for visual display of "1" of the generalized indicators of the state of the controlled object. Communication between processors (computers) is carried out according to information, which is often of considerable volume. At the same time, each processor (computer) is equipped with the necessary volume of individual random-access memory, the required set of input-output and information display devices (n. Fig. 1 is not shown). The transfer of information between processors carried out on the basis of a mailbox) as which blocks 3i-3f, accessible to all processors Ts-1, are used. Dynamic allocation of the memory block between the processors is carried out according to the clock signals of the synchronization unit 5, which is generated cyclically and alternately at the 2- (n + 1) outputs of this unit with a period t, which can be equal to the average time between the adjacent computers references 1) and processors to the memory blocks. Using the clock signal from (j + l) -ro output (, n) of block 5, coming through channel 2j to j-th processor 1j, the latter interrupts its operation and reads and analyzes the contents of state register 6. The contents of register 6 are determined by 24 triggers 19 and 14, respectively, of the sign of occupation and the sign of transmission of adapters, each of which in register 6 is assigned two digits (the first is for a sign of state, the second is for a sign of transfer). The presence of logical zeros in both bits assigned to i-M (, m) by adapter 4 indicates that the corresponding i-th memory block 3 is free to write. If both bits are in the state of a logical unit, this indicates that the corresponding memory block contains information addressed to another processor, and not to the one that receives the clock signal. If only the first of the bits is in the state of a logical one, this is an indication that the corresponding memory block is busy exchanging with another processor. If the state of the logical unit is only the second bit, this is a sign that the corresponding memory block contains information addressed to this processor. Depending on the listed versions of the contents of register 6, the following modes of exchange of the processor with the memory blocks are possible. Record-read mode, processor 1 enters this exchange mode when there are unallocated blocks / memory (state of logical zero of the corresponding bits of register 6) if it is necessary to expand the amount of RAM in this processor or when there is a need for information stored in this block (for example, common to the entire sub-program library system). In this case, the processor can capture from one to several memory blocks. Let such a free memory block be the first memory block 3, and the clock signal go to the first processor 1, which requires an expansion of the RAM. According to the clock signal, processor 1 sprinkles the code into block 8, according to which a capture pulse arrives at the first output of the first group of its outputs and arrives at the first input of the trigger 20i of the first adapter 4. The trigger 20 switches to the control unit 2 memory to channel 2 of the I / O processor C, thereby ensuring the possibility of two-way exchange of information between them. The capture pulse simultaneously enters through the second 10 and Fifth 13 elements OR to the input of the installation of the trigger 19, which, after switching, supplies to the register 6 the recognition status of the memory block 3, which is stored until the end of the interchange on the information between the processor 1 and 3. block, memory. At the end of the exchange, the processor C sends to block 8 a code that, on the first output of the second group of its outputs, generates with a memory release pulse, a post of packings to the reset input of the trigger 20 which, after switching, switches off the memory 3 using the switch 21 channel 2 processor 1. At the same time, the release pulse goes through the third PI of the sixth 18 elements OR to the reset input of the busy sign trigger 19, which, having switched, transmits to the system status register 6 a sign of the release of memory block 3. The number of simultaneously connected to this processor is 1.-block 3. The memory is determined by the address field of the processor allocated for such a connection. Transfer Mode. This exchange mode differs from that indicated by the fact that upon completion of filling with the data of the captured memory block 3, processor 1 addresses this memory block to a specific other processor. The addressing occurs when the next clock signal arrives at processor 1, through which it is via the buffer register 7 and the first element OR 9 of the first adapter 4 enters the relative additional code of a number equal to the position of the addressable processor relative to the given (in this example, first) addressing processor. This code arrives at the information inputs of the counter 16. Then the processor 1 into the block 8 carries the code by which the pulse of the free memory block is generated, which disconnects the memory block 3. from the processor C. The latter issues a code into block 8, by which the the transmission pulse, received through the fourth element SHSh 12 to the reset input of the trigger 14 I of the transmission flag, which having switched, transmits to the system status register 6 a sign of information transmission recorded in memory block 3. At the same time, a transmission pulse from the output of the fourth element OR 12 is fed through the fifth element OR 13 to the input of the installation of the trigger 19 for the sign of occupation and the input for the record of the counter 16. The trigger 19, having switched, transmits to the state register 6 an indication of the occupation of the memory block. According to the signal received at the input of the record of counter 16, an additional code of the relative address of the processor-recipient of information is entered into it. In this case, a non-zero state signal appears at the output of counter 16, which opens the first AND 15 element to pass clock pulses from the first output of synchronization unit 5 to the counting input of counter 16. The passage of clock pulses from the first output of synchronization unit 5 to the synchronization input counter 16 continues until it is reset, which occurs simultaneously with the arrival of the interrupt clock of the addressable processor. In this case, the zeroing signal of the counter 16 is fed to the input of the first element 15 and the input of the one-shot 17. The element 15 and is blocked, and the flow of clock pulses to the input from the synchronization of the counter 16 is stopped. At the output of the one-shot 17, a pulse is formed, which through the sixth element SH-18 enters the reset input of the trigger 19 of the busy feature. The trigger 19, having switched, removes the sign of the memory block 3 (leaving the transfer sign unchanged), therefore the address processor 1. recognizes that the data contained in the memory block 3 is assigned to it, and proceeds to exchange information with it in the Record mode. Reservation mode. This mode is different from the Transfer mode in that the additional code number of processors 1 in the computer system is entered into the counter 16. This means that this processor 1 addresses the information contained in memory block 3 to itself, i.e. reserves a block of memory 3 for itself. This mode is used when it is necessary temporarily instead of this memory block 3: (for the same address field) to connect another processor block 3 to processor 1. Information is exchanged between the processor I and the memory unit 3 via the input and output channel 2 using the switch 21 (Fig. 4). Switching on the switch 21 is performed by a signal from the output of the corresponding trigger 20, which is supplied to the chip select inputs (VC) of the bus driver 25. Bus B is switched with the bus driver C busbar 25 with this signal, which allows outputting information from channel 2 to unit 3 The processor issues an address first. The second part of the message, consisting of the address of the memory block and the address of the word, which through channel 2 and the switch 21 arrive at the inputs of the address selector 27 and the word address register 31, respectively. Then, from the processor I, the synchronization signal of the active SILT device is sent to the address selector 27 to the synchronization input of the trigger 30, to the installation input of which the signal from the output of the address comparison unit 29 is equal to a logical one in the event that the address issued from the processor 1 the memory block coincides with the address of this memory block stored in register 28. If this happens, the trigger 30 is set to the state of the logical unit and at its output (the output of the address selector 27) a signal is generated to the memory block selection inputs (WB) and preparing the memory elements for receiving or transmitting information. At the same time, the signal from the output of the address selector 27 prepares the first 32, third 34 and fourth 37 elements to pass the signal I. The signal from the output of the address comparison block 29 also goes to the gate of the input of the word address register 31, recording the address part of the data, specify the address of the word located in the memory elements. The parallel code of this address from the output of the register of the word address 31 is fed to the address inputs (BP) of the memory elements. If processor 1 writes information to memory block 3, then it via I / O channel 2 and switch 11 outputs the information word code, followed by the Output signal, which goes to the information recording inputs (ZP) of all memory elements. The information word enters the information inputs of the elements (j memory and is written into them by the address set at their address inputs (LD). Clocking the recording of the memory elements at input T is effected by the signal generated by the coincidence of the signals , selection of the Vyshod and SIL memory unit with a delay relative to the signal Output determined by the delay element 36. The signal from the output of the latter simultaneously through the open second element I 33 enters the bus select input (HS) of the tire driver It has 25 switches 21 and one of the bits of the bus A. According to the signal at the inputs of the high-voltage bus drivers, the I / O buses B are connected to the input buses A, and the signal from the output of the fourth element I 37 goes through channel 2 to processor 1 as a passive synchronization signal SIP device confirming the normal completion of the exchange operation. If processor 1 reads information from memory block 3, after issuing the address part, it issues an Input signal coming through the open first AND 32 element, OR 35 element, delay element 36 and open the fourth element I 37 on the clock inputs of the elements 26., - 26p of memory, lack of a signal. The output of these elements at the PZ inputs translates them into the mode of issuing information word bits (at the Q outputs) located in them at the specified address. From the outputs of Q elements 26–26jj of memory R, the bit information word enters the buses A of the bus drivers of the corresponding switch 21. The signal from the output of the delay element 36 through the open second element 33 goes to the inputs of the bus drivers of the switch 21, switching it to The output of information exposed on buses A through bus B to channel 2 of the I / O of the corresponding processor 1. At the same time, this signal goes through switch 21 to the processor as an SIP signal. This completes the input to processor 1 of the selected word of information from memory block 3.

FIG. 5 shows an example of the technical implementation of the control output unit 8. The matching unit 38 is built similarly to the switch 21 and differs only in the selection of the crystal inputs (VC) at zero potential, which ensures that the matching unit 38 is ready to output information via channel 2 of the I / O from the processor |. At first, the address part is output, :: holding the address code of block 8. This code is fed to the input of the address selector 39 and is accompanied by a STR signal. At the output of the address selector 39, a block select signal appears, the AND 40 opening element.

Then, the information word arriving at the setup inputs of the register 41 and accompanied by a signal is output, which through an open element 40 arrives at the installation input: at zero r of the register 41 and through the delay element 42 at the strobe input of the register 41, recorded it from the processor of the code of the information word. At the outputs of the drivers, connected to the bits of register 41, into which the code of the logical unit is entered, pulses are generated, acting on the output of block 8. The number of bits of the register 41 is corresponding to The required number of command pulses is valid, and the code that is defined determines all possible combinations of their simultaneous generation.

Similarly, the control signal output unit 8 (there are no shapers 43), the Address selector 39 and the pulse shapers of the pulse output unit are executed similarly to the address selector 27 (Fig. 4) and the pulse generator 23 (Fig. 2), respectively. .

0 The state register 6 is constructed from functional blocks (matching unit 38, register 41, selector, address 39). Reading information from it is carried out in a similar way.

5 NIN) information from 3 memory blocks.

The installation of the functional units of the system into the initial state (resetting the counters 16, setting the triggers 19 and 20 to the zero state and the logical unit of the triggers 14 of all adapters does not require additional connections and is performed by the initial start-up of the D-1 processors.

Examples of the technical implementation of the main functional units of the computing system (Fig. 2-5) are Q specific and are oriented to linking to the I / O channel of the General Bus type, similar to the channel. microcomputer, however, the principles of building the most computational. multiprocessor systems are with more general (Fig. 1) and applicable when using other types of processors or computers.

Thus, the blocks with the above connections introduced into the multiprocessor computing system allow to significantly increase the speed of information exchange between processors when transmitting large

volumes of data. five .

- Ш1-; 1I-

22

jLjyij-

Gb pp p p p p p

five

and

L

   .CHP / ft

- -K5flOKaM4i ... ff,

To blocks 1, ... / l coofnffemcmSeffHO

./f Salary

Mr-Lg 7,

g

7

to zlak h

urjAai lfln

Fig-3

WT

Phage

Claims (1)

DEVICE FOR COMMUNICATION OF PROCESSORS, containing m memory blocks, m adapters, a synchronization block, the first output of which is connected to the synchronization inputs of the adapters, the first information input — the output of the i-ro adapter (i = l, m) is connected to the input-output of the i-ro block memory, η buffer registers of the control code, where η is the number of connected processors, the input of the j-th buffer register (j = l, n) of the control code is connected to the output of the input-output channel of the j-ro processor of the same name, characterized in that, for the purpose of increase information processing productivity due to exchange of information through shared memory blocks, the status register and η control signal output blocks are entered into it, the output of the jth buffer register is connected to the jth inputs of the control code of all adapters, the input j-ro of the control signal output block is connected to the channel control output input / output of the j-ro processor, (5> 1) -th output of the synchronization unit and (j + D-informational output of all adapters are connected to the synchronization input of the input-output channel of the j-ro processor, the output of the busy indicator and the output of the transmission sign i -ro-adapter connected to the corresponding the corresponding inputs of the state register, the output of which is connected to the information inputs. I / O channels of all processors, i-e outputs of memory capture, memory deallocation, signs of j-ro signal output unit up-. the equalities are connected to the same jth inputs of the i-ro adapter, each adapter containing the first to sixth elements OR, element AND, counter, one-shot, busy trigger, transfer trigger, η capture triggers, η switches, whose first inputs and outputs are are combined and are the first information input-output of the adapter, the second inputs and outputs of the switches are · j + l) -MH information inputs and outputs of the adapter and are connected to the information inputs and outputs of the input-output channels of the j-ro processor, respectively, the input is the j-ro switch is connected to the j-ro capture trigger output, je the adapter control code inputs are connected to the inputs of the first OR element, the output of which is connected to the information input of the counter, the synchronization input of which is connected to the output of the And element, the first and second inputs of which are connected with the synchronization input and with the counter output, respectively, the j-th capture inputs of the adapter memory are connected to the installation inputs of the corresponding jx capture triggers and to the inputs of the second OR element, the output of which is connected X to the first input of the fifth OR element, the output of which is connected to the installation sign of the trigger of the busy indicator, the output of which is the output of the indicator of busy adapter, je the adapter memory release inputs are connected to the reset inputs of the corresponding j-χ capture triggers and to the inputs of the third OR element, the output of which is connected to the first input of the sixth OR element and to the input of the installation 'trigger of the transmission tag,' the output of which is the output of the adapter sign of the adapter, the output of the counter is through a one-shot, the torus is connected to the second input of the sixth OR element, you od which is connected to the reset input of flip-flop Allocation feature, j-e adapter transmit feature inputs are connected to the inputs of a fourth OR gate, whose output is connected to the reset input of latch transmission characteristic to the second input of the fifth OR gate and to the input of the counter recording.