SU1517033A1 - Device for interfacing master and slave computers - Google Patents

Abstract

The invention relates to computing and can be used to build high-performance multi-machine computing systems. The aim of the invention is to expand the functionality of the device by eliminating the cases of blocking low-priority controlled computers. The goal is achieved by introducing M triggers 7, arbiter 8, element OR 9, M elements AND 16, M counters 17, M comparison units 18 and encoder 20, which allows servicing of controlled computers in accordance with their priorities, the order of service requests, the length of the generated queue, and the waiting times for service, i.e. implement a flexible resource allocation system. 1 il.

Description

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The invention relates to computing and can be used to build high-performance multi-machine computer-jiHX systems.

The aim of the invention is to expand the functionality of the device by eliminating the cases of blocking low-priority controlled computing machines.

The drawing shows a block diagram of the proposed device.

The device contains an increment register 1, a switch 2, a control register 3, a decoder 4, M blocks 5 of elements AND, M of controlled computers 6, M triggers 7, arbitrator 8, element OR 9, M of state forming nodes 10, This is done from priority register 1 1, request trigger 12, state register 13, first comparison block 14, AND group 15, And 16 element, reversible counter 17 and second comparison block 18, SH 19 element, encoder 20, group 21 elements OR, group of 22 elements AND, output 23 of the setting, output 24 of the strobe, informational course 25, addressable 5 output 26, information output 27, request input 28, interrogation code output 29, status input 30, computer number input 31 and control enable output 32 of computer 33.

The device works as follows.

At the start of operation, the triggers 7, the triggers 12 of the request, the registers 13 of the state and the reversible counters 17 are in the zero state, which indicates that there are no requests for the exchange of information from control computers 6. The registers 11 permanently store codes The numbers of computers 6 indicate the priority of the machines 6 in the system, and these codes can be changed by the control computer 33 during the operation of the system (the installation chains of the codes and the initial installation are not shown).

The exchange of information on the initiative of the computer 33 is carried out as follows.

The tuning command is entered into the register 1 of the increments on the output 23. The state of the register 1 determines the operating mode of the computer 33 s

the operating memory of the computer 6. The state of register 1 through switch 2 at intervals determined by the supply of computer 33 of building signals from output 24 is recorded in control register 3. The sampling signal at the corresponding output of the decoder 4 permits data to pass through the elements And block 5 and, thus, the connection between the computer 33 and the required computer 6. The address address code from the output 26 of the computer 33 enters through the elements And block 5 The address register of the operating memory of the selected computer 6. At the same time, the elements AND of block 5 provide the transmission of synchronization signals and control information from the output 27 of the computer 33 to the computer 6, and The data flow from the output of the computer 6 to the input 25 of the computer 33.

When exchanging information initiated by the computing machine 6 in order to eliminate blocking requests with low priorities and eliminate conflict situations, the device forms a queue of requests and provides information about it to the controlling computing machine 33.

The signals from the exchange requirements from the computer 6 set the corresponding triggers 7 to one. At the same time, the codes of the exchange operations are solved in the state registers 13 of the corresponding nodes 10 (the next task has been solved, information input-output requirement, signals from the computer control system of the computer 6, etc.). Triggers 7 and arbitrator 8 serve to eliminate a conflict situation when several requests are received from different machines simultaneously. 6. Requests fixed by triggers 7 are sent to arbitrator 8, which determines the most priority of them and sets the corresponding trigger 12 to one state. This causes a reset of the corresponding trigger 7, thereby allowing the arbiter 8 to further serve lower priority requests. In addition, the signal from the output of trigger 12 comes through

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element OR 19 to the input 28 of the computer 33, thus indicating the presence of a request. Information on the number of requests received is determined by the encoder 20, and the order in which they are received is recorded by reversing counters 17 of nodes 10.

The order information of requests from the computer 6 is generated on the counters 17 as follows. In the initial state, the contents of all counters is zero (there are no exchange requests from computers 6 in the system). Upon receipt of the first request, the corresponding trigger 12 of the node 10 is set to one state, thereby allowing the passage of signals from the output of the element OR 9 through the element 16 to the incremental input of the reversing counter 17. The content of this counter becomes equal to one and will increase by one a subsequent request from other computers 6; In a similar way, the contents of all the remaining counters 17 are formed, and the earlier value of the request corresponds to a larger value e contents of the corresponding counter 17.

The servicing of requests for the exchange of the control computer 33 is performed as follows. The signal from the output of the element OR 19, indicating the presence of requests from the computer 6, the computer 33 polls the status registers 13 by sequentially submitting 29 polling codes on the output, equal to the numbers of the computers 6, to the outputs of the units 14 comparing nodes 10. In the case of coincidence of the polling code and the number (priority) of the computing machine 6 from the register 11; the exchange operation codes from the register 13 of the state and the next receipt of the request from counter 17 through the element groups AND 15 and OR 21 are fed to the input 30 of the computer 33. The control computer 33 analyzes the entire set of information: the priority of the computer 6, the order in which the request arrives, the length of the queue. After deciding to service the request, the computer 33 initiates an exchange with a selected

3

With this purpose, the corresponding setting command is written to the I register and the output 32 sends an enable signal to the 22 AND group, through which the exchange operation code from the outputs of the 21 OR group is written to the control register 3. Further

the exchange initiated by the computer 6 is carried out in the same way as an exchange initiated by the computer 33.

When servicing a request from computational small 6, codes from the corresponding reversible counter 17 through groups of elements 15 and 15 and 21 and 22 are sent to all units 18 of the comparison of nodes 10, where they compare

with the contents of your own counter

17 each node. If the contents of the counter 17 of the order of arrival of a request from this computer 6 are greater than the contents of the counter

17 of the serviced computer 6, then the corresponding block

Comparison 18 generates a signal that reduces by one the contents of this reversible counter

17. Thus, the queue is compressed during out-of-order servicing (when servicing requests in the order of their arrival, the queue is not compressed, as in the system

there is no counter 17 with a larger code value than counter 17 of the serviced computational machine 6). At the end of the service, the computer 33 is set to the initial (zero) state trigger request 12, the state register 13 and the reversible counter 17 of the corresponding state signal generating unit 10.

Claims (1)

Invention Formula A device for interfacing control and controlled computing machines, containing the increment register, switch, control register, decoder, M blocks of elements AND three groups in each, element 11PI, group of elements OR, group of elements AND, M of nodes of forming state signals, each of which consists of state register, request trigger, priority register, first comparison block and group trigger 71 elements, and the information input of the increment register is the device setup input, the information output of the increment register is connected to the same input of the switch, the output of which is connected to the input Record-reading of the control register connected by its output to the input of the decoder, the i-th output of which where ... M is connected respectively to the first inputs of the elements AND of the three groups of the i-Vo block, the second inputs of the elements AND of the first and second groups of each of the M blocks are respectively the address and information inputs of the device TWA, the outputs of the elements of the first and second groups of each of the M blocks are respectively the address and information outputs of the device from the first to the second, the second inputs of the elements of the third groups of each of the M blocks are the first through the M-th information inputs of the device, the outputs The elements of the third groups of each of the M blocks are connected to the information output of the device, the control input of the switch is the input of the device Strobe, the information input i-ro (where ... M) of the state register of the state signaling node is i- The operation code of the device, the output of the state register of the i-th generation node of the state signals is connected to the first input of the elements of the i-th generation node of the state signals, the second inputs of which are connected to the output of the first comparison unit of the i-th state generating signal node , the first input of which is connected to the output of the priority register of the i-ro node forming the state signals, the trigger output of the request of the 1st generating unit of the state signals is connected to the i-th input OR element, the output of which is the output of the device request the outputs of the elements AND groups of the i-ro node of the state signal formation are connected to the i-th inputs of the elements of the OR group, the second input: the first comparison blocks of all the node (the state signal stateing is the input code of the control number my computing device, eight u 5 0 5 30 d five 0 0 five the outputs of the elements OR of the group are connected to the second inputs of the elements AND of the group and are the output of the device state, the input of the device resolution is the first input of the elements AND of the group whose outputs are connected to the information inputs of the control register, characterized in that in order to extend the functionality of the system due to the exclusion of cases of blocking low-priority controlled computers, M triggers, an arbitrator, the second OR element, an encoder, and, in each of M nodes, signal generation with This is an And element, a reversible counter and a second comparison unit, the i-th input of the device request being the installation input of the i-th trigger, the output of which is connected to the i-th input of the arbiter, the i-th output of which is connected to the i-th input The second element SH and with the installation input of the trigger request i-ro node forming the state signals, the output of the second element OR is connected to the second inputs of the elements AND of each of the M nodes forming the state signals, the output trigger request i-ro node generating the state signals connected to trigger reset input, the first input of the element And the i-ro node forming the state signals and the i-th input of the encoder, the output of the element And the i-ro node generating the state signals is connected to the incremental input of the reversing counter of the i-th node generating the state signal, the output of which is connected to the first the input of the second block of the i-ro node forming the state signals and to the second inputs of the elements AND groups of the i-ro node forming the state signals, the output of the second block comparing the i-th node forming the state signals is connected to the decrement input of the reversible About the counter of the i-ro node generating the state signals, the second input of the second comparison unit of the i-ro node generating the state signals is connected to the output of the corresponding AND group element, the output of the encoder is the output of the controlled computer number of the device.