SU1223203A1 - System for checking electronic timepiece - Google Patents

Abstract

The invention relates to microelectronic computing and can be used to control electronic clocks. The purpose of the invention is to increase the reliability of the control of electronic clocks. The device contains a generator 1 of the reference frequency, a divider 2 with a variable division factor, time counters 3i-3, logic OR 4 and AND 5i-5, 1, triggers 6 and 7, delay line 8 and memory 9. The control keys 10 | and 10 ", RS flip-flops lli-11", storage devices 12i -12 ", key transistors 13i-13", dongle 14, inverters 15 and 16, multi-input logic circuits And 17 and 18, control mode off transistor 19, the transistor 20 includes the control mode and the transistor 21 controls the filling of the counters 3. The introduction of new elements and the formation of new connections between the elements of the device make it possible to ensure the multiple filling of all the counters and control the transmission of the information signal between them. For Q to reduce the monitoring time, the divider 2 SS is made with a variable division factor. 1 3. Clause f-ly, 1 ill. (L Control input 1chE ND 00 o oo

Description

The invention relates to the field of microelectronic computing and, in particular, can be used to control electronic clocks.

The aim of the invention is to increase the reliability of monitoring of electronic clocks by ensuring multiple filling of all counters and controlling the transmission of the information signal between them, as well as reducing the time of monitoring.

The drawing shows a block diagram of the electronic watch control system.

The system contains sequentially on. alternating frequency generator and variable divider 2, time counters, logic circuit OR 4 and AND 5i-5 „1, triggers 6 and 7, delay line 8, memory device 9, control keys lOi-10„ , RS-triggers 11-11 ", operational memory, devices 12i-12", key transistors 13i -13 ", protection key 14, inverters 15ji 16, multi-input logic circuits And 17 and 18, transistor 19 off control mode , the transistor 20 includes the control mode and the transistor 21 controls the filling of the counters 3. And the output of the divider 2 through the security key 14 is connected to a serial chain consisting of the first control key lOi and the first time counter 3i, the second key 102 and the second Over counter, etc. The outputs of the 3i-Zge time counters are connected to the S-inputs of the corresponding RS-flip-flops „ . The R-inputs of which and the OR 4 circuit, as well as the outputs of the AND 5i-5 "1" circuit, are connected to the second input of the corresponding control keys lOi-10 ". The outputs of the RS-flip-flops are connected to the inputs of the corresponding random access memory, the outputs of which are connected respectively to the first input of the OR 4 circuit and to the first input of the AND 5i-5n-i- circuits. The input of the first random access memory 12 is connected to the second input of the first And 5 circuit the input of the second to the second input of the second circuit AND 5, the entrance of the penultimate random access memory to the second input of the last circuit AND. The input of the last random access memory 12p is connected to the inputs of delay line 8, respectively, of the first circuit n 17 and the first trigger 6, the output of which is connected via the second trigger 7 to the second input of the circuit n 17, whose output is connected to the input through transistor 19 memory device 9 and with the third input of the control keys 102-Yul, except for the first key 10, and with the second input of the divider 2. The output of the delay line 8 through the inverter 15 is connected to the control input of the dongle 14, and through the transistor 21 neither the counters are filled to the output of the inverter 16, the input of which is connected to the zeroing inputs of the flip-flops 6 and 7. Between the storage device 9 and the output of the inverter 16, the control mode activation transistor 20 is turned on. Output

the trigger 7 is connected to the second input of the Rish 4 circuit, the third input of the circuit P17 through the circuit P18 is connected to the corresponding information outputs of the time counter 3i. The output of the dongle 14 is connected to the fourth inputs of the lOi-10 control keys, except for the first key 10, and the key transistors 13i-13p are connected between the outputs of the respective operational storage devices 12i -12 "and the control input of the security key 14.

The system works as follows. A logical single signal is applied to the control input of the system. This single signal zeroes triggers 6 and 7 and simultaneously enters the inputs of the inverter 16,

0 the output signal of which opens the monitoring mode switching transistor 20 and the filling control transistor 21 of the counters 3i-3p. The output signal of transistor 20 is supplied to memory 9 and overwrites the information on its

 conclusions. Usually a logical unit is recorded in it before the start of monitoring, so after overwriting, a logical signal appears at the output of device 9 (if, when the system is turned on, the recording in the memory

Q device 9 corresponds to a logical "O, then in this case the monitoring mode is set automatically without the influence of the control input signals). This zero signal goes to divider 2 with a variable division factor and the lOg – yd control keys. The signal in divider 2 alters the division ratio by eliminating the corresponding number of triggers. The magnitude of the division factor is 2, where n is the number of triggers to be excluded. Due to this, it becomes possible to reduce the monitoring time, since the frequency of the counting pulses at the output of divider 2 changes in proportion to the division factor. This same zero signal opens the 102-Yul keys, which pass the counting pulses from generator 1 to the corresponding time counters 3i-3n. In this case, the signal from the output of the counter-controlling transistor 21 is inverted by the inverter 15 and fed to the control input

0 of the dongle 14, as well as the key transistors 13i - 13l, which are opened and overwrite the output zero memory level with a single output signal at their output. Under the influence of a signal on

5 of the control input of the dongle 14, the latter is closed for a time sufficient for. rewriting the operational storage devices 12 and blocks at the same time

five

the arrival of counting pulses from the output of divider 2 to counters 3i-3 ".

A single signal from the output of the operational storage devices 12i-12 is fed to the first inputs of the logic circuit OR 4 and AND 5. Moreover, the second input of the circuit OR 4 receives a zero signal from the output of the zeroed trigger 7. The second input of all the circuits AND 5 is supplied with a zero signal the inputs of the corresponding operational storage devices. Then at the inputs of the OR 4 circuit there are zero and one levels, which means that a zero opening signal is obtained at the output of the circuit. At the inputs of the first and other schemes And 5 there are also single and zero signals, but at their output they receive an already closing single signal. This means that the first key lOi is in the open state, while the remaining control keys 102-10l are closed. Therefore, the counting pulses arrive only at the first counter 3i, which is filled or backfilled (depending on its state at the time of control) until it is completely filled. Then, a single level appears at its output, which is fed to the S input of the first RS flip-flop lli, the output of which is fed to the input of the first random access memory 12i and rewrites the information in it again, forming the logical "O, and the entrance is “1. In this case, two zero signals are present at the inputs of the OR 4 circuit (from the output of flip-flop 7 and the output of the overwritten first operational memory 12i), so a single signal appears at the circuit output that closes the first control switch lOi and stops the counting pulses the first counter Z.V. at the same time, at the inputs of the first circuit AND 5 there is a single signal from the input of the first random access memory 12 | and the unit level already present from the output of the second storage device 122. As a result, a zero signal is generated at the output, which now opens the second control key 102, and only the second counter 32 of time begins to fill. The process of successively filling the counters 3i - 3rt continues until the last counter 3 is filled, while the information transfer between them Hfe occurs. Thus, for the first monitoring cycle, the system brings all the counters to the same initial state (in this case, to complete filling).

However, it may happen that when the power is turned on, a single signal automatically appears at the output of the individual counters, but in fact the counters remain unfilled, i.e. there is a false signal.

filling In order to eliminate such a reason for reducing the reliability of monitoring the clocks, a second cycle of filling the counters is provided without transferring information between them. This cycle starts immediately after the last counter is filled, which is confirmed by the single output signal of the last RS flip-flop 11. This single signal is fed to the input of trigger 6, the input of the multi-input circuit nI 17 and the delay line 8. In this case, the state at the output of the flip-flop 6 changes, but the flip-flop 7 is still zero, since at its input only the leading edge of the tilting pulse is formed after the first cycle. Therefore, a zero signal arrives at the second input of the OR 4 circuit. From the delay line 8, the single signal is inverted by inverter 15, and the key transistors 13i -1313 reopen, which overwrite the information in the operational storage devices 12i -12 ", at the output of which logical" 1 appears, and at the input - "O. The filling of the counters is repeated as in the first cycle. After refilling the last counter 3, the unit level from the output of the last RS flip-flop 11 is returned to the input of flip-flop 6 and overturns it. In this case, a pulse is formed at the input of the trigger 7, and at its output, instead of the zero signal, a single signal appears, which arrives at the second input of the OR circuit 4. At the same time, as in the previous cycles, the key transistors 13i - 13n are opened and the information in the operational memory is overwritten devices 12i- 12 ". Then, at the inputs of the OR circuit, there are two single signals, and at the output, an opening zero signal appears. The first key lOi opens, and the first counter 3 | starts counting. After its filling, the information of the first random access memory is overwritten, namely: “O” appears at the output, “1. Then for the OR 4 circuit, one zero and one single signal will occur. At the same time, at the output its zero level does not change and the first counter 3i begins to refill. It is periodically filled until the output state of the trigger 7 changes from one to zero. After rewriting information in the first random access memory 12i. At the inputs of the first circuit And 5 there are two unit levels, and at the output of it a zero signal is formed, which opens the second key 102. Then, parallel to the filling of the first counter 3i, the second counter 32 is filled. After filling it, the second memory is overwritten, and the second control key 102 is closed, since one input of the first circuit AND 5 receives

logical "About from the input of the first random access memory 12i and" About - from the output of the second memory 122 after their corresponding rewriting. As a result, a single level appears at its output. Then the third key is opened, since the inputs of the second logic circuit And 5 have single levels, and all other keys, except the first, are closed. The first and third counters are simultaneously filled. This counting process continues until the first and last 3-; 3 counters are simultaneously filled. Thus, the first counter 3 counts the pulses arriving at all the remaining Z-3 counters, including itself, i.e. its content is the sum of the contents of all Z-3p counters. Knowing the number and capacity of 32-3 meters used in hours, it is easy to determine in advance for them the total amount of pulse counting that can be used later as a checksum. Comparing the checksum with that obtained on the first counter B after filling all the counters in the pulse counting mode (the third control cycle), is realized by the second multi-input n I 18 circuit. If these sums coincide, a single logical signal is generated at the output of the third input And 17. On the other inputs of this circuit, there are already single logical levels from the output of trigger 7 and the output of the last RS flip-flop 11p, so a logical zero signal appears at its output, which opens transistor 19 turned off control mode, overwrites the memory 9 from a zero level to the unit. A single signal of the device 9 transfers the system from the monitoring mode to the current time counting mode, since this signal removes the interlocking transmission of information between the counters and blocks the flow of counting pulses to them directly from the divider 2.

When 3i-3p meters are filled in the current-time counting mode, the transfer from the counter to the counter occurs and a corresponding change in the information in them. If a

If there is a violation of the signal transmission between the counters, this fault is easily identified by the absence of a change in the state of the corresponding counters.

The result of the control can be displayed on an indicator board connected to the control output.

Claims (2)

Invention Formula . An electronic clock control system containing n time counters, an OR circuit, an n-1 And circuit, two triggers, a delay line, a memory device, and 5 5 0 o 5 0 five about five Consequently, a reference frequency generator and a divider, characterized in that, in order to increase the reliability of the control, n control keys, n RS-flip-flops, n random access memory, a dongle, two inverters, two multi-input logic circuits n and , the metering control transistor, the turn-on transistor, and the control mode cut-off transistor, and n key transistors, the divider output being connected via a dongle to a series circuit consisting of a first control switch The key and the first counter, the second control key and the second counter, the p-key and the p-counter, the outputs of the counters are connected to the S-series of the corresponding RS-flip-flops, the R-inputs of which are connected to the second inputs of the control keys and in the corresponding circuits And and the OR circuit, the outputs of the RS-flip-flops are connected to the inputs of the corresponding random access memory, the outputs of which are connected to the first inputs of the corresponding AND circuit and the RSHI circuit, while the input of the first random-access memory is connected to the second input of the first circuit we And, the input of the second - to the second input of the second circuit And, the penultimate input to the second input of the last circuit And, and the input of the last operative memory device is connected to the input of the delay, the first multi-input circuit nI and the first trigger, the output of which through the second trigger is connected to the first input of the first multi-input circuit pI, the output through the control-switching transistor disconnected to the memory input, the third input of control keys, except the first key, and the second divider input, the output of the delay line through the first inverter connected to the control input of the dongle and through the meter filling transistor to the output of the second inverter connected to the zeroing inputs of the first and second triggers, the output of the second inverter connected to the memory output, the output of the second trigger connected with the second input of the OR circuit, the third input of the first multi-input circuit n And through the second multi-input circuit n And connected to the corresponding information outputs of the first account ika time the security key output is connected to fourth inputs of actuating keys other than the first key, and outputs the operational storage devices via corresponding switching transistors are connected to a control input of the security key. 2. The system according to claim 1, characterized in that, in order to reduce the monitoring time, the divider is made with a variable division factor.