RU1812636C - Frequency divider having variable division factor - Google Patents

Abstract

Application: the device relates to pulsed technology and can be used in artoth synthesis systems. SUMMARY OF THE INVENTION: a frequency divider with a variable division coefficient contains: pulse counters (1, 2, 3) coincidence elements (4. 5, 10), RS triggers (6, 7, 8), delay element (9). shaper (11) of short pulses, controlled electronic key (12), D-trigger (13). a device (14) for resetting to zero memory elements, an input and output bus (15.16) with corresponding communications. 2 il .. - -: - V

Description

go

about

with

ON

The invention relates to a pulse technique and can be used as a high-speed frequency divider of digital systems for the synthesis of stable frequency networks and also as an element of digital phase locked loop systems used in transmitting and receiving devices.

The purpose of the invention is to improve operational reliability.

By introducing a reset device to zero memory elements, a synchronous D-flip-flop, a delay element and a controlled electronic key, a pulse shaper with corresponding links in the considered divider with a variable division coefficient after turning on the supply voltage and ending the recording of the initial information in the first and the third pulse counters, the first RS-flip-flop is reliably set to the correct (zero) initial state, due to which the correct initial state of the first and second elements with fall, and reliable operation of the divider as a whole.

In FIG. 1 is an electrical functional diagram of a variable divider divider; in FIG. 2 are timing diagrams explaining the principle of operation of the device.

The considered divider with a variable division coefficient contains the first, second third counters 1, 2, 3 pulses, and the transfer outputs of the first and third counters 1, 2, 3 are connected to their preset inputs, and the counting inputs of the first and second counters 1, 2 through the first and second matching elements 4 and 5 are connected to the input bus.

The transfer output of the first counters 1 is loaded on the installation inputs to the unit of the first and second RS-flip-flops b and 7, the installation input to the unit of the third RS-flip-flop 8 is connected to the transfer output of the third pulse counter 3, which is connected through the delay element 9 to the installation input in zero of the first RS trigger b. The transfer output of the second pulse counter 2. is connected to the counting input of the third counter 3, the direct and inverse outputs of the first RS trigger 6 are connected to the second (control) inputs of the second and first matching elements, respectively. The direct outputs of the second and third RS flip-flops 7 and 8 are connected to the first and second inputs of the third matching element 10. The output of the third matching circuit 10 is connected to the inputs of the zero and second setting

RS-flip-flops 7 and 8 and with the input is formed. tel 11 short pulses.

In addition, between the input and output of the delay element, a controlled

electronic key 12, control input

which is connected to the synchronous output

 D-flip-flop 13, and reset input to zero

of this trigger, as well as reset inputs to zero

first, second and third counters 1,2,3

pulses, connected to the reset output to zero of memory elements 14. The clock input of the synchronous D-trigger is connected to the output of the delay element 9, and its information input is connected to the logical bus

5 units;

The third input of the third coincidence element 10 is connected to the input bus 15, and the output of the short pulse generator is connected to the output bus 16. code

0 buses 17 and 18 are connected to the information inputs of counters 1 and 3, respectively. Consideration of the operation of the proposed divider with a variable division coefficient should begin from the moment of switching on the supply voltage, since the correct operation of the divider is determined by the correct initial installation of the RS-flip-flops 8, 7 and 8 after switching on the supply voltage. .

0 when the source is turned on and there is no input signal, which is a sequence of unipolar pulses (Fig. 2, a}, the states of the mentioned RS-flip-flops will be determined by the states of the 5 outputs of the transfer counters 1 and 3, as well as by the signal level output of match element 10. As for the signal at the output of match element 10, in the absence of an input signal it will have

0 is high, and the signals from the transfer outputs of the first 1 and third 3 counters can be either zero or single. To eliminate this ambiguity, a device 14 is introduced into the proposed divider

5 to reset the memory elements to zero, the output of which is connected to the zero inputs of the counters 1, 2 and 3, as well as the synchronous D-trigger 13. When the power source is turned on, neither the reset device 14 generates

0 a short positive pulse, which ensures that the synchronous D-trigger 13 is set to zero, the memory registers of the counters 1 and 3 are cleared, and the decimal counter 2 is set to zero.

5, the controlled electronic key 12 is in the open state, and the counter transfer output 3 will be connected to the zero input of the RS flip-flop b through the delay element 9. which can be implemented as an asynchronous D-flip-flop,

Clearing the memory registers of counters 1 and 3 will provide the appearance at their outputs of transferring low-level signals that are fed to the inputs of the RS-flip-flop 6 (Fig. 2 b, c). This is the so-called forbidden combination for the RS-flip-flop with inverse control, therefore, at the outputs of the RS-flip-flop 6 there will be high signal levels (Fig. 2, d, e).

RS flip-flops 7 and 8 under the influence of low-level signals from the transfer outputs 10 of counters 1 and 3 (Fig. 2, e, and), as well as a high-level signal from the output of coincidence element 10 (Fig. 2 g, k) are initially set in a single state (Fig. 2, h, l).

Since the transfer outputs of the counters 15 1 and 3 are connected to their preset inputs, due to the influence of low-level signals on these inputs from the transfer outputs to the counters 1 and 3, information is recorded with information — 20 inputs of each counter.

After the end of the recording cycle of this information, high (single) signal levels are established at the outputs of the transfers of the counters 1 and 3. In this case, the state of the second and 25th third RS-flip-flops 7 and 8 does not change (Fig. 2 h, l), and the state of the first RS-flip-flop 6 must necessarily become zero, since only in this case the element match 4 will be opened, and the element СОВ-30 of fall 5 will be closed, which is necessary for the correct operation of the device in the division mode, i.e. providing a predetermined division coefficient starts already from the first division cycle .35

Setting the RS-flip-flop b to zero or single state is determined by which of the two inputs S and R the signal of the unit level is earlier received, which comes from the counter transfer output 40 1 in the first case and from the counter transfer output in the second. 3 (Fig. 2 b, c).

In the prototype device, where there is no delay element 9, everything is determined by the duration of the information recording cycles in counters 1 and 3. If the information recording cycle in counter 1 is longer than in counter 3, then the RS-trigger b will be set to one - the state of coincidence 5 will be open and open, which will lead to improper operation of the divider in the mode of dividing the pulse repetition rate. However, in the opposite case, if the duration of the information recording cycle in counter 3 is longer than in counter 1, there may be 55 malfunctions in the correct installation of the RS-trigger b, because, firstly, this duration is far from strictly fixed, which may when replacing meters, and secondly, it varies with changing environmental conditions. In addition, the time interval A t between the time of setting counter 1 to the initial state and the time of setting counter 3 may be shorter than the time required for switching the RS-trigger 6, and this will also lead to malfunction and malfunction of the pulse frequency divider .

Due to the presence in the proposed scheme of a divider with a variable division ratio of the delay element 9, it is possible to reliably set the required state of the first RS-trigger b, which, as mentioned above, after turning on the supply voltage and ending the recording of information in the counters 1 and 3, it must be established to the zero state. In order to reliably achieve this goal, the delay time r3 of the delay element 9 (Fig. 2 c) should be selected based on the amount of time required to install the first RS-trigger 6, and the possible spread of the parameters of the counters 1, 3 and the effect should be taken into account environmental influences.

Thus, thanks to the introduction of the device 14 to reset the memory elements and the delay element 9 to zero with their connections in the proposed circuit after the end of the transient processes caused by turning on the power source, cleaning the TAM elements and then writing the information to the pulse counters 1 and 3 , at the transfer outputs of the latter, high level signals are established, the second and third RS flip-flops 7 and 8 will be in the single state, and the first RS-flip-flop will be in the zero state. It should be emphasized that, unlike the prototype device in this circuit, the correct information on the frequency division coefficient will be recorded in the counters 1 and 3 already in the first division cycle. This is ensured by forced zeroing of all memory elements when the power is turned on using a special device 14, which in the simplest case is a logical inverter with a master RC circuit at the input connected to the power source. Along with resetting the counters 1,2 and 3, the synchronous D-trigger 13 is also reset to zero, which is designed to control the electronic key 12. In turn, closing this key deactivates the delay element 9, which is necessary in the proposed circuit only at the initial start-up phase of the divider. After the initial reset of D-flip-flop 13 at

when the power source is connected, the key 12 is opened due to the low level signal being sent to its control input from the output of the trigger 13. However, immediately after the information is written to counter 3, the positive voltage drop appearing at the transfer output of this counter is transmitted through delay element 9 to the clock input of the D-flip-flop 13 and switches it to a single state. The high-level signal from the output of this trigger goes to the control input of the electronic key 12, which closes and excludes the delay element 9 from the circuit. During further operation of the divider, the state of the D-trigger 13, due to the presence of a level 1 signal at the D-input, does not change and, therefore, the delay element 9 does not affect the operation of the divider.

Since the first RS flip-flop b is in the zero state as a result of connecting the power, match element 4 is open and match element 5 is locked. This means that in the first half of the cycle of dividing the pulse repetition rate of the input signal, the counter 1 will operate, the counting input of which will receive 4 input pulses through the open coincidence element (Fig. 2, a). At the same time, counter 1 and counter 3 can work both on subtraction and on summation. Hereinafter, it will be considered that a subtraction mode is selected.

Since two of the three inputs of matching circuit 10 will be set to single levels of signals from the outputs of the second 7th and third 8 RS-flip-flops (Fig. 2, 3i l), the first input pulse (Fig. 2, a) will pass through coincidence inverting element 10 at the inputs of the zeroing of the second 7 and third .8 RS-flip-flops, and through the device for normalizing the pulse duration 11 will go to the output device. Ori this, as can be seen from FIG. 2h, l, said triggers 7 and 8 are set to the zero state.

Subsequent input counting pulses, like the first one (Fig. 2, and) in the first half of the frequency division cycle through the open coincidence element 4, are fed to the counting input of counter 1, in which binary information about the number of units in decimal is recorded at the stage of preset equal to the value of the coefficient. division of the counter. Since the number of these units can be 0-9, the minimum binary number that can be written in counter 1 is -00002 (Oy), and the maximum is 1001a (9io). Thus, counter 1 operating in the first half of the division cycle must be binary decimal.

Since counter 1 operates in the subtraction mode, after the number of pulses (Ne / 0io, equal to the decimal equivalent of the binary number recorded in this counter, arrives at its counter input, counter 1 is completely cleared and the signal is low level (Fig. 2.6), which sets the triggers 6 and 7 to a single state (Fig. 2, b-h).

In this case, a single signal is established at one of the input of match element 10, and under the action of the signals from the outputs of the first RS-flip-flop 6 (Fig. 2d), match element 4 is closed and match element 5 is opened. The second half of the frequency division cycle begins, when the input pulses arrive at the counters 2 and 3 connected in series. The first one, counter 2, has a constant

a coefficient of dividing the frequency of the incoming pulses, equal to ten, and the second counter 3 is a counter with preliminary recording of information and may, like counter 1, have a different conversion factor for the pulses arriving at its input. This combination of counters 2 and 3 allows you to organize the count not of the number of units, but of the number of tens received at the input of the pulse divider.

At the information inputs of the counter 3, a binary code of dozens of Mdes, a division coefficient of a frequency divider with a variable division coefficient, is supplied. As a result, the division coefficient Kdel

the proposed divider can be determined from the ratio

Kdel (Me) yu + (MDes} 10-th +12,

where (Med) u and (MDes) u are the decimal equivalents of binary numbers installed on the information inputs of pulse counters 1 and 3.

Since a binary counter can be selected as the counter 3 operating, like counter 1, for subtraction, it is obvious that the maximum division factor of the proposed divider will be determined as high as possible

conversion factor of this binary counter. For example, when choosing a standard counter 155IE7, KSCh 16 as the counter 3 and the maximum division ratio of the proposed device is 171.

In the second half of the frequency division cycle, the counting pulses through the open coincidence element 5 are fed to the input of the counter 2, which for every ten input pulses will respond with one output pulse from the transfer output.

The pulses from the output of counter 2 are received at the counting input of counter 3, in which the code Mde is recorded. After cleaning the counter, i.e. after in the second half of the division cycle (Mdes) 10 10 counting pulses are received at the input of the divider, the negative voltage drop will appear at the output of the transfer of counter 3, which will set the third RS-trigger 8 to the single state (Fig. 2 and kl), and the first RS-trigger 6 to the zero state (Fig. 2 c, d, e).

It is important that at this stage the delay element 9 is already turned off from operation, since otherwise, with a zero code of units (K | units at 0), the signal of setting the RS-trigger 6 to one from the transfer output of counter 1 could get ahead of the setting signal this trigger to zero. This would undoubtedly lead to a violation of the operating mode of the divider and the establishment of one or more cycles of the erroneous value of the division coefficient.

By disabling the delay element 9 using the controlled electronic key 12, the RS flip-flop b will be reliably set to zero at any value of the co-factor Ned and will unlock the first coincidence element. 4 unlock the second coincidence element 5. In addition, thanks to When the third RS-flip-flop 8 is set to single state, high level signals will be set already at the two inputs of the third coincidence element 10. Thus, the circuit is prepared for the next division cycle.

The end of the previous division cycle and the beginning of the next coincides with the arrival of the first, after capsizing to the zero state of the RS-flip-flop 6, of the counting pulse - (Fig. 2 a, d, e). Since at this moment in time triggers 7 and 8 are in a single state, creating high-level signals at the two inputs of coincidence element 10, the indicated counting pulse passes through the three-input coincidence element 10 and then through the pulse duration normalization device 11 goes to the output of the divider (Fig. 2 m). In addition, the signal from the output of coincidence element 10 (Fig. 2g, k) sets the triggers 7 and 8 to the zero state. . :

Subsequently, the operation cycle of the proposed divider with a variable division ratio is repeated.

Formula, invention A frequency divider with a variable division coefficient, containing the first, second and third pulse counters, moreover, the inputs of the preset of the first and third pulse counters are connected to their transfer outputs, and the information inputs of these pulse counters are connected to the corresponding

0 to the code buses, the input bus is connected through the first and second matching elements to the counting inputs of the first and second pulse counters, respectively. but, the transfer output of the second pulse counter5 is connected to the counting input of the third pulse counter, the second inputs of the first m of the second coincidence elements are connected respectively to the inverse direct direct outputs of the first RS-flip-flop, S0 inputs of the first m of the second RS-flip-flops are connected to the output the transfer of the first pulse counter, the S-input of the third RS-trigger is connected to the transfer output of the third pulse counter, the direct outputs of the second m of the third RS-triggers are connected respectively to the first and second inputs of the third coincidence element, the third input of which is connected to the input bus, the output of the third element is coincidentally 0 connected to the R-circuits of the second and third RS-flip-flops. also containing an output bus, characterized in that, in order to increase the reliability of the functionalized, a device is inserted into it

5 reset to 0m memory elements, O-flip-flop, delay element, short-pulse shaper, controlled electronic key, and the reset device in O-memory elements is connected to the installation inputs in O of the first, second and third pulse counters, as well as D -trigger, n delay element is connected between the transfer output of the third pulse counter and the R-input of the first RS-trigger,

5, the information input of the controlled electronic key being connected to the transfer output of the third pulse counter, the output to the output of the delay element, and. control input - with the output of the D-trigger,

0 D-trigger clock input is connected to the output of the delay element, and its information .. The input input is connected to the logic bus

units, between the output of the third element

match output bus - enabled

5 shaper of short impulses.