SU1211785A1 - Multichannel device for reception of signals - Google Patents

Description

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The invention relates to the digital processing of information modulated signals in real time to determine their parameters and can be used in communication systems and data transmission.

FIG. 1 shows a block-c: sema multi-channel device for receiving signals; in fig. 2 - shaper sequence of odd numbers / in FIG. 3 is a synchronizer in FIG. 4 - shaper reference signals; in fig. 5 - decisive block. The device (Fig. 1) contains a converter 1 analog-code, a synchronizer 2, a shaper 3 reference signals, elements 4, - 4 EXCLUSIVE OR, - shapers 5, 5 sequences of odd numbers, drives 6 - 6jj, a decisive unit 7.

The fopflofator (Fig. 2) of the sequence of odd numbers contains a binary counter 8 and an adder 9.

The synchronizer (Fig. 3) contains a generator of 10 pulsed pulses and a counter 11.

The shaper (Fig. 4) of the reference signals contains the generator 12 of the reference signals and converters analog-code 13.

The decision block (Fig. 5) contains comparators 14, switches 15 and a decoder 16.

The device works as follows.

The process of calculating the sum of squares of the differences between the received and reference signals occurs in m cycles. At the beginning of each measurement cycle (conversion of the received signal to a code), a short pulse is generated at the output of synchronizer 2, on the leading edge of which a preset of all triggers (not shown) of the shaper of an odd-numbered sequence to the unit state occurs, and on the trailing edge - starting of the converter 1 analogue code and imager 3 reference signals. Simultaneously, the second output of the synchronizer 2 generates a sequence of pulses that acts throughout the measurement cycle, clocks the operation of the analog-code converter 1, and generates 3 reference signals and elements (the last link is not shown).

2117852

In the process of measuring the current sample of the received signal from the output of the converter 1 analog-code synchronously with the clock pulses

5, the unitary code (burst) of the current sample of the received signal arrives at the first inputs of elements 4, and the unitary code of the current reference signal of the corresponding reference signal arrives at the second inputs of elements 4–4 synchronously with the clock pulses from the corresponding outputs of the driver 3 of the reference signals. At the same time in each

 By channel 5, the output of element 4j is a unitary code equal to the absolute difference between the absolute current values of the received and reference signals.

20 For each pulse arriving at the input of the generator of a sequence of odd numbers, it counts odd numbers and transfers their codes to drive 6,

25 where odd-numbered codes are added to a previously accumulated amount.

Thus, in each measurement cycle, the proposed receiver provides simultaneous execution of operations for obtaining the absolute differences of the received and reference signals in the elements 4, -. 4, summation in accumulators 6 to 6 codes of odd numbers to obtain squares of these differences and summing the obtained squares of absolute differences.

After tti measurement cycles at the outputs of accumulators 6, -6, the sum codes of squares of absolute differences between the received signals and reference signals are obtained. These codes from the outputs of the accumulators 6, -6 "are transmitted to the decision-making device 7, where the smallest code is determined, according to which the received signal is identified with that of the reference (possibly transmitted) signals, for which this code is the smallest.

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Shaper 5; The sequence of codes of odd numbers (Fig. 2) contains a binary counter 8 and an adder 9, the output of the counter 8 is connected to the second input of the adder 9; starting from the second bit, and the first input of the adder is connected to the input of the counter.

Shaper 5; The sequence of codes of odd numbers (Fig. 2) contains a binary counter 8 and an adder 9, the output of the counter 8 is connected to the second input of the adder 9; starting from the second bit, and the first input of the adder is connected to the input of the counter.

The shaper 5j works as follows.

Before the receiver is started, all the triggers of the counter 8 are preset to one. Upon receipt of the first pulse from the output of element 4; in each channel, all the triggers of the counter 8 are reset to the zero state and the unit is added to the first digit of the adder 9; which is added to the zero state code of the counter 8 and transmitted to the accumulator 6. On each received next pulse from the output of the counter 8j, the binary code is taken, which is fed to the second input of the adder 9, starting from the second bit, which ensures the operation of multiplying the code by two. Simultaneously with the arrival of the code, a unit is entered at the second input of the adder at the first input (first discharge). In addition, for each pulse. arriving at the input of the counter 8 and at the first input of the adder 9.-, at the output of the adder 9, j, an odd number code is obtained, which is added in the accumulator with the previously accumulated codes of sequences of odd numbers.

The drive 6 is made in the form of accumulating adder.

The synchronizer 2 (Fig. 3) contains a series-connected clock generator 10 and a pulse counter 11,

Synchronizer works as follows.

The generator 10 generates a sequence of clock pulses. These pulses are fed to the input of counter 11, which divides the frequency of the generator pulses by a factor equal to the number of quantization levels in amplitude. The signal at the output of counter 11 corresponds to the measurement interval.

The shaper 3 reference signals (Fig. 4) contains a generator 12 of reference signals and converters 13 - 13 "analog-code, the inputs of which are connected to the corresponding outputs

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the reference signal generator 12, and the outputs are outputs of the reference signal generator 3. The input of the generator 12 reference signals connected to the output of the counter 11 of the synchronizer 2,

The reference signal generator 12 (FIG. 4) is triggered by the falling edge of the short pulse, which forms the counter 11 (FIG. 3). The reference signals from the output of the generator 12 pos. blunt to the 13 j 13 “analog-code converters, which convert analog reference signals into discrete signals represented in the unitary code.

The decisive block (Fig. 5) contains K (K fog 7 1 where n is the number of channels) of series-connected blocks containing comparators 14 and switches 15. In each 4th block the number of comparators and switches is equal to n / 2 to the nearest whole number .

The decision block works as follows.

Codes will accumulate (oil 6, - & "arrive at comparators 14, - 14" and switches 15, - which pass the code of the accumulator, which as a result of pairwise comparison turned out to be smaller. The outputs of the comparators of each block and KOhOiapaTopa 14 of the last block go to the input of the decoder 16 and represent the encoded number of the accumulator, the output code of which is the smallest.

At the output of the decoder 16, an excited state of the tire is obtained, the number of which corresponds to that identified with the received reference signal.

Thus, the proposed device has a smaller volume

equipment and great speed. Compared to the prototype, it allows the processing of higher-frequency received signals while performing conversion and processing operations.

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Claims (2)

1. MULTI-CHANNEL DEVICE FOR RECEIVING SIGNALS, containing a synchronizer, the output of which is connected to the control inputs of the analog-code converter and the driver of the reference signals, in each information channel of the drive, the outputs of which are connected to the corresponding inputs of the deciding unit, the output of which is the output of the device, the information input of the converter the analog code is the input of the device, characterized in that, in order to improve the speed of the device, an element And is introduced into each information channel KEY OR or odd number sequence generator, EXCLUSIVE OR element output connected to the information input of the odd number sequence generator, whose output is connected to the drive input, the synchronizer output is connected to the control inputs of the odd number sequence generator of information channels, the analog-code converter output is connected to the combined first the inputs of the elements EXCLUSIVE OR information channels, the outputs of the driver of the reference signals are connected with the corresponding the existing second inputs of the elements EXCLUSIVE OR information channels. 2. The device according to p. ^ Characterized in that the decision unit contains a comparator, groups of comparators, groups of switches and a decoder, the outputs of the comparators of each group are connected to the first inputs of the corresponding switches of the same group and with the corresponding inputs of the decoder, the outputs of each pair of switches of the previous group are connected respectively with the first and second inputs of the comparator of the subsequent group of comparators and the second and third inputs of the switch of the subsequent group, the outputs of the switches of the last group are connected to the first, second inputs of the comparator, the output of which is connected to the last input of the decoder, the first and second inputs of the comparators of the first group are combined with the second and third inputs of the switches of the first group, respectively, and are the input of the decider, the output of the decoder is the output of the decider. _а 3_и _т , 1211785