SU1598190A1 - Device for dividing signals in multichannel systems - Google Patents

Abstract

The invention relates to communications and can be used in multichannel systems for transmitting binary code with time division signals. The aim of the invention is to increase the speed and noise immunity of the transmission. This goal is achieved by introducing on the transmitting side of block 12 registers, block 7 decryption, block 6 elements And, adder 11 and digital-analog converter 8, and on the receiving side - block 17 registers, adder 18, block 24 decryption, generator 13 clock pulses, an extractor of 16 sync pulses, an analog-to-digital converter 22, a subtraction unit 14, a storage unit 21, a counter block 15, a threshold block 23, and a block of 25 elements I.

Description

The invention relates to communications and can be used in multichannel systems for transmitting binary code with time division signals.

The aim of the invention is to increase the speed and noise immunity.

transfer.

FIG. Figure 1 shows the block diagram of the transmitting side of the device; in fig. 2 is a block diagram of the receiving side of the device.

The device contains on the transmitting side a multiplier 1, a master oscillator 2, a shift register 3, an element OR 4, a shaper 5 sync pulses, a block of 6 elements I. A decryption unit I, a digital-to-analog converter 8, first 9 and second 10 Low-pass filters, the adder 11 and the register unit 12, and on the receiving side - the generator 13 clock pulses, the subtraction unit 14, the counter block 15, the selector 16 clock pulses, the register block 17, the adder 18, the shift register 19, the multiplier 20, the storage unit 21, analog -digital converter 22, threshold b Lok 23, block 24 decryption and block 25 elements I.

The device works as follows.

The moved binary code from each source is successively fed to the first inputs of the block of 6 elements AND O Block 7 of the decryption alternately ... but with a time interval

sd

with

00

with

T G / Q,

where l is the pulse duration;

Q - the number of intervals on which

divides C,

permits passage of each bit of the message sources to the input of the element OR, The resulting binary sequence from the output of the element OR sequentially enters the shift register 3 and shifts in it with the time interval T. The values of the function Y (t) for times t, t T, t, + 2Т, о .., t - Qt (Q 1, 2, 3 ...) are calculated previously by the formula

but

Y (t) A, -I.Ytt - (m - D-Tjx

TPH

hehrС- / Ь -Т (ha -, de m is the sequence number of the pulse,

Y (t) BO-cosif (t). a (t),

a (t) exp (t), i

(f (t) I w (t) -dt, to (t)

 cO expC- -t) i

“,. 1 41nc, 0 2wfoV / b

-o-g

, - 1 22

with

c is the number of times a (t) and (xiCt) change,

fg is the average frequency of the spectrum Y (t); and are stored in the form of parallel M-partition codes in block 12 of registers.

The values of the function are calculated from the moment of time corresponding to dY (t) / dt max and equal to

moreover, the sine function for Y (t) is zero at this point. As a result, in multiplier 1, the binary multiplication of the binary sequence by the corresponding values of the function Y (t) occurs. Multi-input adder 11 during each T outputs to the channel through a digital-to-analog converter 8 and the first low-pass filter 9 a signal

 k., ..,; Y (k.T),

five

0

five

0

where X- is the bit value of the i-th source.

To ensure synchronization of transmitted and received values and q, the master oscillator 2 in each clock interval T generates a synchronization pulse, which is fed to the input of the clock generator 5, which generates a synchronization signal from the square wave pulse for transmission over the communication channel and transmits through the second filter 10 low frequencies in a specific bandwidth per channel. The outputs of the master oscillator are used to synchronize the operation of the blocks by the transmitting side of the device.

At the input of the receiving side, the selector 1b of sync pulses generates a synchronization signal that triggers a generator of 13 clock pulses. A pulse appears at the output of the 13 clock pulses, allowing the operation of the analog-digital converter 22, which converts the signal and j j into digital form and transmits to the subtractor 14. Vlok 1 subtraction subtracts from the signal 1}, the value of the simulated signal U

M, 1

 and

k.i

and.

five

Q

50 55

Since this is a binary code, each T may contain 2 different values of U p; . When the next storage unit receives one of the codes and p, j in the next T, after its reading, a binary parallel code appears, the number of bits of which means the presence of the corresponding bit of the binary sequence. In each T from the output of the storage unit, 21 units of the corresponding bits are added (or not added in the case of zero) to the contents of the corresponding counters. Before the next clock cycle begins, the contents of each j-ro counter (where j is 1,2,3 ...., L) are rewritten into (j + 1) counter, after which the first counter is reset.

Thus, after L clock cycles, the number of ones in the leftmost L-M counter accumulates, which is equal to the number of times when this bit is defined as a unit. If it is the number of units

of them

frequencies

more L / 2. then the threshold unit 23 forms a unit at the output, if it is less than or equal to L / 2 - zero.

From the output of the threshold block 23, the value of the generated bit is entered into the shift register 19, after which the multipliers 20 perform the operation X Y (k-T) and feed these values to the multi-input adder 18.

The operation of units 19, 20, 17, 18 of the receiving part is completely similar to the operation of units 3, 1, 25 and 21 of the transmitting side. The code from the output of the threshold unit 23 is supplied to the second input of the block, 5 digital-to-analog converter and

14 subtraction. Who in every t

ten

the outputs of the block of registers are connected to the second inputs of the residents, the outputs of which are connected to the signal inputs of the adder, the outputs of the decryption unit are connected to the first inputs of the block of elements And, which moves are connected to the inputs

an OR element whose output is connected to the second input of the register; the shift from the second to the fifth outputs of the master oscillator is connected respectively to the input of the decryption unit, to the clock inputs of the adder, to the second input

ka 14 subtraction, which in each produces the subtraction of this code from the code from the analog-digital converter 22.

The values of the binary sequence from the output of the threshold unit 23 are fed simultaneously to the first inputs of the block 25 of elements AND, in which the received bits are divided along the corresponding channels. A clock generator 13 controls the operation of the 2k decoding unit. The latter has a number of outputs equal to the number of channels to be divided, while the outputs are alternately activated for a time T and allow passage. the discharge of the binary sequence is corresponding to the recipient of the messages.

Claims (1)

Invention Formula A device for separating signals in multichannel transmission systems, containing multipliers on the transmitting side, first and second low-pass filters, OR element, clock generator, serially connected master oscillator and shift register, whose outputs are connected to the first inputs of multipliers, and on the receiving circuit - multipliers , the sync pulse selector, and the shift register, the outputs of which are connected to the first inputs of the multipliers, characterized in that, in order to increase the speed and noise immunity ivosti transmission, on the transmission side incorporated registers unit, a decryption block elements and ,, serially connected adder and digital to analog converter whose output is connected to the input of the first filter nizh20 25 thirty 35 to the input of the sync driver, the output of which through the second low-pass filter is connected to the first low-pass filter and is the output of the transmitting device, the inputs of which are the second inputs of the AND block, and the adder, deciphering unit, clock generator, sync pulse generator, serially connected analog-to-digital converter, subtraction unit, and remembering unit, sequentially connected meter block, threshold unit and unit block And, the second inputs of which are connected to the outputs of the decoding block, the outputs of the block are connected to the second inputs of multipliers whose outputs are connected to the signal inputs of the adder, whose output is connected to the second input of the subtractor, the outputs of the memory block are connected to the counter inputs 40 of the counter block, the output of the threshold block is connected to the signal input of the shift register, the output of the clock pulse is connected to the input of the clock pulse generator, the outputs of which are connected to the input of the decryption unit, to the second input of the storage unit, to the third input of the subtraction unit and to the clock inputs of the register, shift , The block counters and analogue-digital converter whose input is connected to an input of the sync select L and is input signa nym receiving apparatus side reference input and outputs cat swarm are respectively a second input of the threshold unit and output unit elements I. 45 50 55 598190 of them frequencies -, 5 digital-to-analog converter and ten the outputs of the block of registers are connected to the second inputs of multipliers, the outputs of which are connected to the signal inputs of the adder, the outputs of the decryption block are connected to the first inputs of the block of elements And, the outputs of which are connected to the inputs the OR element, the output of which is connected to the second input of the shift register, from the second to the fifth outputs of the master oscillator are connected respectively to the input of the decryption unit, to the clock inputs of the adder, to the second input 0 five 0 five to the input of the sync pulse generator, the output of which through the second low-pass filter is connected to the output of the first low-pass filter and is the output of the transmitting side of the device, whose inputs are the second inputs of the AND block, and on the receiving side a register block, an adder, a decryption block, clock generator, clock extractor, serially connected analog-to-digital converter, subtraction unit, and storage unit, serially connected meter unit, threshold unit, and block of elements And, the second input. dyas are connected to the outputs of the decryption unit, the outputs of the register unit connected to the second inputs of multipliers, whose outputs are connected to the signal inputs of the adder, whose output is connected to the second input of the subtractor, the outputs of the storage unit are connected to the counting inputs 0 of the counter block, the output of the threshold block is connected to the signal input of the shift register, the output of the clock pulse connected to the input clock generator, the outputs of which are connected to the input of the decryption unit, to the second input of the storage unit, to the third input of the subtraction unit and to the clock inputs of the register with motor, counter block and analog-digital converter, the input of which is connected to the input of the clock extractor and is the signal input of the receiving side of the device. The main input and output of which are, respectively, the second input of the threshold block and the outputs of the block of elements I. five 0 five i l m I