SU1200233A1 - Digital averaging meter of time intervals - Google Patents

Description

The invention relates to measuring technique and can be used in systems for automatically measuring the duration of the time intervals between pulses 5 "Start" and "Stod", coming through two different front tires.

The purpose of the invention is to improve the accuracy of measurement! The device at the expense of weakening the dependence of the relative measurement error on the measured value Ζ _ο by deriving (carried out automatically in the measurement process) the number η of averaged time intervals, in the process of measurement, depending on the size of the measured interval ι _ο .

Figure 1 shows the block diagram of the device; figure 2 is an example of the execution of the logical unit of the meter.

The meter contains a clock generator 1, six keys 2 - 7, the element

8 delays, logic block 9, counters 10 and 11, decoder 12, triggers 13-15, comparator 16 and register 17.

The output of the clock generator 1 is connected to the operating inputs of the keys 2,3,

4 and 7, as well as through the delay element 8 - with the fourth input of the logic unit 9. The outputs of the keys 2 and 3 are connected respectively to the summing and subtractive inputs of the counter 11, the output of the key 4 - to the zero inputs of the trigger 13 and 14, as well as to the summing input counter 10, the output of the key 7 is connected to the subtractive input of the counter 10. The control inputs of the keys 2,3 and 4 are connected to the corresponding outputs of the decoder 12 connected by the inputs to the outputs of the trigger 13 and 14, the single inputs of which are connected respectively to the outputs of the keys 5 and 6, working which inputs are respectively, the “Start” and “Stop” inputs of the meter, and the control inputs are connected to the inverse output of the trigger 15. The outputs of this trigger are connected to the first and second inputs of the logic unit

9, the third input of which is connected to the output of the comparator 16, and the code input - to the code output of the counter

10. The first output of the logical block

9 is connected to the single input of the trigger 15 and to the input “Receive” of the register 17, the second output - with the zero input of the trigger 15 and with the input “Reset” of the counter 11, and the third output - with the input: “Shift” of the register 17. Code output

the counter 11 is connected to the information input of the register 17 and to the first information input of the comparator 16, the second information input of which is connected to the bus of the initial code setting.

The clock generator 1 generates ^ at the output short pulses of high stable frequency with a period T%. Keys 2-6 are normally closed: the pulse arriving at the key's working input passes to its output only if there is a single signal at this time at the control input 15 of the key; Key 7 is normally open: a pulse arriving at its working input is passed to the output only in the absence of a single signal at the control input of the key (prohibition element 20).

The delay element 8 delays the pulses by a time ^ 8, which is sufficient to trigger the counter 10, $ - <Τ _ο .

To describe the operation of logic ²⁵ block 9, we denote the state of the trigger 15 by 3 ₅ , the output signal of the comparator 16 by A, and the contents of the counter 10 by x. All outputs of block 9 are pulsed, pulses for 30 of them are generated synchronously with the clock pulses arriving at the fourth input of block 9 through delay element 8, depending on the values of A, Z _e and ί.

35 The impulse on the first output of block 9 is formed only when 3 "= 0, when the number x has the form of an integer power of two, i.e.

x = 2 ^C at k = 0.1, ..., (w - 2)

⁴⁰ (1)

(t is the number of digits of the counter 10), and, moreover, A = 1, or when £ (regardless of the signal A, but with 5 ₃ = 0).

The impulse at the second output of block 9 is formed only when 5 "= 1; x = 0 regardless of signal A.

The impulse at the third output of block 9 is formed only when ⁵⁰ 3 ₅ = 1, х - 2 ^К - 1, к = 1,2, ...,

(w - 1).

These logical functions can be implemented, for example, by a block whose structure is shown in FIGS. 2, ⁵⁵ where: 18 - 21 are elements AND, 22 - 24 are elements OR, 25 is a decoder. The output bus of the decoder corresponding to the case x = 0 (a single signal on

3

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four

which is present at x = 0) ^ connected to the input element And 18, tires, corresponding to x = 2 ^K at k = 0.1,

..., (t - 2), is connected to the inputs of the OR element 23, the bus .. the corresponding ί = 2 is connected to the input of the element OR 22, and the tires corresponding to x = 2 - 1 at k ⁼ 1,2, ··· ,

(t - 1), - with the inputs of the element OR 24.

Counters 10 and 11 are reversed | θ. The decoder 12 has potential inputs and outputs. Denote by 8 (and the status of the 13 "" I * flip-flops, respectively. The single signal and the output of the decoder connected to the _{5 controlling input of the key 2 is present only at 8d = 1, 5 _g = 0; on the exit connected to the control switch of the key 3 , only at 5 ± = 0,

3 ₄ = 1, at the output, connected to the up- _2θ by the entrance of the key '4, only when> 4 ⁼ 1, 8} ^ 1.

Triggers 13 - 15 - regular short-circuit triggers with separate inputs, trigger | 5 triggered on the falling edge 25

good momentum.

Comparator 16 maintains a single signal on gain if the condition is met

(g) thirty

tse £ - the contents of the counter 11,

. £ * - the number supplied to the second information input of the comparator 16.

Register 17 is made shift. Im-35 hive, arriving at the entrance "Reception" of the Gistr, records in it the contents of the counter 11; the impulse arriving 1 input "Shift" shifts the contents of the system by one bit towards 40

disastrous discharges.

The principle of operation of the device is as follows. During each of. : time intervals of a clock pulse form, the number of which> 45 пропор {is proportional to the length of the x-th interval (x - 1,

...). The sum of £ values of на, accumulated in the counter 11. In this mode (accumulation mode) the device works 50

as long as the condition (2) is not reached. After this, the accumulation of the sum £ either stops, whether the condition (2) is fulfilled with the inversion of the quantities ^- · with the number x, 55 m of the form (1), or continues until the interval T / with the smallest validation of x, having the form (1) , or,

if inequality (2) cannot be met, continues until the end of the interval (for Ζ _ο 0).

The number of averaged intervals, the greater the smaller

(for a fixed number £ *). The value of n, i.e., the number of averaged intervals, is fixed by the counter 10 (only the values of n, having the form 2 ^{K, are used} ).

After completion of the accumulation mode, the device goes into division mode, in which the accumulated sum £ is divided by η by transferring the contents of counter 11 to register 17 and to shifting the contents of the register towards the lower digits ..

The device works as follows.

In the initial state, all the triggers 13-15 are set to zero, while the keys 2,3,4 and 7 are closed, and the keys 5 and 6 are open; register 17 and counters 10 and 11 are also set to zero, and the second information input of comparator 16 is supplied with a code combination encoding the number £ *> 0. Thus, in the initial state, 3 ^ = 3 ₄ = 5 ₃ = 0, A ~ x = £ - 0. At the same time, the clock pulses arriving at the fourth input of logic block 9 from the output of delay element 8 do not pass to any of its outputs.

Suppose first that all Γ; > 0. The first input pulse of the device arriving at the Start bus and the fixing time of the beginning of the interval Г ,, set the trigger 13 to one-unit, as a result, the key 2 opens, and the clock pulses start the post from the generator 1 output to the summing input counter 11. The impulse arriving on the bus "Stop" and the fixing time of the end of the interval _? sets trigger 14 to unit, as a result, key 2 closes, and key 4 opens, so the next clock pulse from generator 1 output, passing through key 4, adds one to counter 10 and returns triggers 1.3 and 14 to zero, i.e. the device returns to its original state with the difference that the counter 11 now records the number N4, proportional to the value of q, and in the counter 10 - the number x of processed intervals, x = 1,

Let ₄ <£ *, i.e. when processing the first interval the output signal

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five

comparator 16 does not occur. The second, third, etc. intervals, 1. $, ... are processed similarly, in the counter 11 the sum Ν ^ + Ν ₂ + is formed

+ and in the counter 10 - the number

ί = 2,3, ... Suppose that the condition (2) is satisfied when processing the ί, ί interval, i.e. at the output of the comparator 16 there is a single signal. If this value of ί satisfies condition (1), then the clock pulse of the end of the interval ΐ; returning triggers 13 and 14 to zero and ensuring the fulfillment of condition (1), passing through delay element 8, will go to the first output of logic block 9, transferring the contents of counter 11 to register 17 and setting the third trigger 15 to one, putting this device into 20 divisions.

If the number of the interval X; , during the processing of which the condition (2) is reached, does not satisfy condition (1), the device continues to operate in the accumulation mode, i.e similarly to the specified, the following time intervals are processed until condition (1) is reached, after which the device ³⁰ switches to the division mode (a pulse appears at the first output of logic unit 9).

If _{1 0} b 0, then condition (2) is not fulfilled, in this case, after processing-35 ki ή ~ 2 ⁴ input intervals (the maximum possible number for a given capacity of the counter 10), the device switches to the division mode (trigger 15 is set to one / ^ in spite of the fact that the signal at the output of the comparator 16 is absent.

The division mode is implemented as follows.

In any case, regardless of ⁴⁵ polnekiya You are a condition (2), the device goes into division mode only when the value of n equal to an integer power of two.

For ⁵⁰ measurement result must be divided value Nij £, accumulated in the counter 11 and transmitted to the register 17, ^K 2, which may be accomplished by shifting the contents of the register 17 to discharge at Stora? 55 LSBs well.

Since the installation of the trigger 15 in the unit keys 5 and 6 are closed,

6

blocking by the time of division the input pulses of the device, which could distort the result of the averaging, and the key 7 from—

₅ closes, the clock pulses from the output of the generator 1 begin to flow to the subtracting input of the counter 10. The first of these pulses changes the contents of the counter 10 from 2 * to 2 * - 1,

10 due to which the same clock pulse delayed by element 8 for the time of response of counter 10 will pass to the third output of logic unit 9, i.e. to the input "Shift" register 17, 15 causing the displacement of its contents by one digit in the direction of the lower digits, i.e. dividing this content into two. With a further decrease in the content of the counter 10, a shift pulse is formed each time a number of the form 2–1 is in the counter (except for the case k = 0). When the equality ί = 0 is reached, a pulse is formed at the second output of logic block 9, the counter 11 and the trigger 15 returning to zero} the device returns to the initial state with the difference that register 17 now contains the measurement result obtained using the formula ί = - --Σί \, where

η 1

the value of η is equal to either the minimum number x, under which conditions (1) and (2) are satisfied, or the number 2 ^^, if condition (2) cannot be achieved.

If condition (2) is already reached when processing the first time interval (we get A = 1), then after the first pulse arriving at the summing input of counter 10 (end clock ΐ,), we get ί = 1 = 2 ^e , as a result the same pulse, delayed by element 8, passes to the first output of block 9, transferring the contents Ν of counter 11 to register 17 and setting trigger 15 to one; to the third output of block 9 (i.e., the pulse does not pass to the "Shift" input of register 17), since the trigger 15 is triggered by the falling edge of the clock pulse (i.e., the element 21 of block 9 opens after the end, the pulse at its working input The next clock pulse, after passing through the opened key 7, sets ΐ = 0 and, after passing through the delay element 8, enters the second output of block 9, returning to zero

7

counter 11 and trigger 15. Thus, when η = 1, the contents of register 17 are not shifted.

The device works in the same way with I; <Oh when the input pulses

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"Stop" is received earlier than the pulses at the "Start" input, the only difference is that the numbers числа, ·. clock pulses arrive

5 to counter 11 through key 3.

I200233

From 16

-

Reset

From 15

Sbgyg

with in

l

T ~ 7 ------ _Ί Ζ 2 3 ·% t-2 ί • * one

25

7GT

2 ^t - '· /

-J

\.

Ogg flea 10 fig. 2

Claims (2)

DIGITAL AVERAGE MEASURING TEMPORARY INTERVALS, containing a clock generator, the output of which is connected to the inputs of the first, second and third keys, the control input of the last of which is connected to the first output of the decoder, and the output - to the combined zero inputs of the first and second triggers, the outputs of which are connected to the inputs the decoder, the second and third outputs of which are connected to the control inputs of the first and second keys, respectively, the outputs of which are connected respectively to the summing and subtracting inputs of the first about the counter, which is different because, in order to increase the accuracy of measurements, a second counter, a logic block, a register, a delay element, three keys, a comparator and a third trigger, the direct output of which is connected to the first input of the logic block, are entered into it, second entrance Which is connected to the inverse output of the third trigger and control inputs of the fourth, fifth, sixth keys, the output of the last of which is connected to the subtractive input of the second counter, the summing input of which is connected to the output of the third key * · (3 code output - to the code input of the logic unit, the third output of which is connected to the comparator output, the first information input of which is connected to the information input of the register and the code output of the first counter, the clock generator output is connected to the working input of the sixth key directly, and through the delay element - with the fourth input of the logic block, the first output of which is connected to the input “Receive” of the register and to the single input of the third trigger, the zero input of which is connected to the input “Reset” of the first counter and from the second the output of the logic unit, the third output of which is connected to the "Shift" input of the register, whose outputs are the device output buses, the second information input of the comparator is connected to the tires of the meter initial code, and the Start and Stop buses are connected to the working inputs the fourth and fifth keys, respectively, whose outputs are connected to the single inputs of the first and second triggers, respectively.! 1200233 one 1200233 2