SU1171796A1 - Signature analyser - Google Patents

Description

one

The invention relates to computing and can be used in systems for diagnosing digital objects.

The aim of the invention is to simplify the design of the signature analyzer.

The drawing shows a diagram of the signature analyzer,

The ycTpq jcTBo contains informational 1 and synchronizing 2 inputs, encoder 3, summation Mountains A and 4 modulo two, registers 5-, and 5 offsets.

The analyzer works as follows

In the initial state in the register 5, the code 00000000 is recorded (the setting circuits in the initial state are conventionally not shown). The encoder 3, which arrives at the input 1 of the analyzed sequence, converts it into a two-channel ternary sequence. The work of the encoder is presented in the table. Input Outputs

000

101

X 10

Possible and other logic of the encoder. The information from the first output of the encoder is fed to the fifth input of the first modulo-2 adder, where it accumulates with feedback signals from the 7th 9th, 12th, and le-To bits of the shift register. The secondary information from the second output of the digger comes at the fifth input of the second modulo adder.

962

where is added to the feedback signals of the 6th, 8th, 11th, and 15th bits of the shift register. The arrival of a clock pulse is

record the result in the first and second bits of the register, respectively. Thus, the convolution of the analyzed sequence is carried out according to the law of the polynomial F (X)

   X-X + 1, since each coefficient of the primitive polynomial is assigned a certain register bit (Fig. 1). Signal from the second output of the encoder

is added to the feedback signals that correspond to the coefficients of the imperative polynomial, different from zero, a, a. e 1 To perform the convolution of two consecutive bits of information in one clock cycle to the first, second, third, and quarter inputs of the first modulo-2 adder, signals are output from the outputs of those register bits that correspond to non-zero coefficients of a primitive polynomial in the next clock cycle, e. register bit outputs that currently correspond to coefficients

aj and at.

The positive effect of using the present invention lies in its simplifications due to the exclusion from the analyzer circuit of the switch, the trigger, the OR element and the one-shot, which in turn leads to an increase in its reliability.

Claims (1)

A SIGNATURE ANALYZER containing a coder and a signature generator, consisting of a first adder modulo two and sixteen-bit shift registers, the output of the first adder modulo two connected to the information input of the first bit of the shift register, the first, second, third and fourth inputs of the first adder modulo two connected to the outputs of the seventh, ninth, twelfth and sixteenth bits of the shift register, respectively, the information input of the adder is connected to the input of the encoder, the sync input of the analyzer with is one with the clock inputs of the bits of the shift register, characterized in that, in order to simplify the design, a second adder modulo two is inserted into it, the output of which is connected to the information input of the second digit of the shift register, the first second, third and fourth inputs of the second adder modulo two are connected to the outputs of the sixth, eighth, eleventh and fifteenth bits of the shift register, respectively, the outputs of the (21-1) ~ -th bits of the shift register (1ΐ ΐ ί7) are connected to the information inputs of the (2x + 1) -th bits, and the outputs of the 2i-th bits - with and With the information inputs of the (21 + 2) th bits of the shift register, the encoder outputs are connected to the fifth inputs of the first and second adders modulo two. SU-1171796 1 11