SU1167609A1 - Multichannel signature analyser - Google Patents

Abstract

A MULTI-CHANNEL SIGNATURE ANALYZER containing the first group of n modulo-two adders. (n is the number of outputs of verifying digital nodes), n shift registers, the first group of information inputs of the analyzer connected to the first inputs of the corresponding modulators two of the first group, the second input of the i-ro modulo two of the first group

Description

The invention relates to computing and can be used in systems for diagnosing digital objects.

The aim of the invention is to expand the functionality of the device by providing the ability to control simultaneously any number of multi-output digital nodes, not: 1 K.

The drawing shows an example of the device motling for the case Kn 2, F (X) X + xs + 1, Oj (X) X -I-X + 1. The multichannel signature analyzer includes the first 1 and second 2 modulo adders, the first 3 and second 4 registers, the first 5 and the second 6 groups of information inputs, synchronization input 7. The outputs of the analyzer are the outputs of the registers. The outputs of the device can also be used as the outputs of modulo-two adders.

In the initial state, all the registers of the analyzer are in the state O ... 0.

The reset circuits are not shown.

Let the i-e groups of information inputs of the analyzer receive the sequence

A (,, (1) a-, (2) ... a, (t);

BUT; ) a, - (2) ...);

. A, a; J1) a .; (2) ... ai Jm),

where m - the length of the analyzed posledb

abnormalities

or in compact notation - a sequence of vectors

A, -) AU2) ... A (T) ... A; (t)

where A i Crg) a- CJ) a, -SG) ...

(-c) T7i1.

MP

After the passage of m clock pulses in the register of the analyzer, a signature is formed, which would have been obtained in a known device, if its inputs were received by a sequence of vectors

 Hell (1) At (1) ...)

BUT,

AI (2) A (2) ... A (2) ... Ai (m). ). .. Ats (t).

Thus, in each operation cycle of the device in the registers, a code is written which would have been obtained in the prototype in K cycles.

Thus, the proposed device with an insignificant complication, as compared with the known, allows to obtain data signatures coming simultaneously from any number of multi-output digital nodes not exceeding K. In this case, an additional effect is to slow the analyzer's performance by ensuring parallel processing of information simultaneously all KHP inputs.

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Claims (1)

A MULTI-CHANNEL SIGNATURE ANALYZER containing the first group of η adders modulo two (n is the number of outputs of the tested digital nodes), η shift registers, the first group of information inputs of the analyzer connected to the first inputs of the corresponding adders modulo two of the first group, the second input of the i-th the adder modulo two of the first group (2 4 ΐ <n) is connected to the output of the first bit (i-1) -ro of the shift register, the second input of the first adder modulo two of the first group is connected to the output of the first bit of the ηth shift register, bit The e outputs of the Eth shift register (1 E - n) are connected respectively to the group of inputs of the Eth adder modulo two of the first group, characterized in that, in order to expand the functionality by simultaneously controlling any number of multi-output digital nodes, not exceeding K, it contains K - 1 groups of p. adders modulo two, the first input of the i-ro adder modulo two Jth groups .. ·. (2 S3 К) is connected to the output of the (ί - 1) adder modulo two (• 3 - 1) th groups, the first input of the first adder modulo two ϊth groups is connected to the output of the ηth adder modulo two (J - 1) -th group, the second input of the Eth adder modulo two of the Jth group is connected to the corresponding information input of the 3rd group of the analyzer, the group of inputs f-ro adder ^ modulo two 'of the 3rd group is connected to a first group of outputs (Ng - 3 + 1) = x (with Ng - 3 + ^1> 0) bits of respective shift registers, where Ng - number of bits of registers corresponding to non-zero coefficients respectively primitive polynomials, the group of inputs of the Eth adder modulo two of the 3rd group is connected to the outputs of the corresponding adders modulo two (3 - Ng) -ft groups (with Ng - 3 + + 1 ^ 0), the output of the adder modulo two The Jth group is connected to the input of the (K - 3 + 1) th category of the corresponding shift register, and in each shift register, the information inputs of the jx bits are connected to the outputs of the (j - K) th bits, where j = (K ~ 1) , N.