SU1166065A1 - Device for monitoring parameters - Google Patents

Abstract

A DEVICE FOR MONITORING PARAMETERS, containing the number of monitored parameters N sensors. the admission control connected by inputs to the device inputs, the elements NOT, and the decoder connected by the outputs to the inputs of the indicator board, which, in order to simplify the device, it contains the first and second registers, the adder, the counter, the AND element, the first and the second delay elements, a clock generator, a differentiating element, and an OR element, connected; n j -r: I. SlliJiileTEaA. The inputs to the outputs of the sensors of the tolerance control and the information inputs of the first register, and the output to the input of the differentiated element associated with the output (N + DM information input of the first register and with the input of the first delay element connected to the output of the Start of the clock generator and with the zero setting input, connected by a counting input to the shift input of the first register, to the input of the second delay element and to the output of the clock generator, and the bit outputs to the inputs of the AND element connected an output with a Stop input (L clock generator and a second-register enabling input connected to the second delay element output to the clock input, and an information input to the output of the adder connected to the first input with the first register output and the second, third, fourth and fifth) inputs - respectively with the first, second, third and fourth outputs of the second register, connected by sixteen fifth inputs to the corresponding first chipboard inputs of the decoder and to the inputs of the elements NOT connected to the outputs to the second decoder inputs.

Description

The invention relates to technical diagnostics and can be used to monitor the operability and localization of the location of a malfunction of radio engineering objects having arbitrary connections between functional elements.

A multichannel device is known that has a serially connected sensor in each channel, a unification unit 10, a subtraction unit, a comparison unit, a matching element and a measuring key connected to the output of the unification unit, whose control input is connected to the output of the element and 5 a deviation detection and recording unit, the inputs of which are connected to the outputs of the corresponding measurement keys, a unit for setting the nominal values of parameters, the outputs of which are connected to the second inputs of the subtractors,. the block for setting tolerances, the outputs of which are connected to the second inputs of the comparison units, the channel selection block 25, the inputs of which are connected to the outputs of the corresponding subtraction blocks and the outputs to the second inputs of the matching elements IJ.

The drawback of the device is its limited functionality, since the device does not allow to unambiguously localize the location of faults in objects characterized by a multitude of interdependent monitored output parameters.

The closest to the invention in the technical essence is a device containing a group of 40 tolerance control sensors, a group of logical elements NOT, a decoder of state codes of an object of control (OK), an indicator board, and the sensor outputs are connected to the first group 45 of the decoder codes of state codes neither OK and the inputs of logical NOT elements whose outputs are connected to the second group of inputs of the decoder of the OK status codes connected by the outputs to the indicator board.

The device implements a combinational search for failures in the OC and allows unambiguously localizing the malfunction in an object that has arbitrary connections between its elements and, consequently, is characterized by a set of interdependent parameters | 2J.

The drawback of the device is the complexity of the technical implementation of the decoder with a large number of monitored parameters OK, since it is known that the number of information inputs than the complexity of integrated circuits, for example, for a linear type decoder, is determined by the equation

Lf N-Z, (1)

where N is the number of monitored parameters OK.

Taking into account the NOT logical elements necessary to obtain the inversion of input signals, the overall complexity of the decryption node can be estimated by

L, N + N-2. (2)

Hence, it is clear that already with several tens of controlled parameters, the technical implementation of the decryption node and the device as a whole becomes difficult to implement.

The purpose of the invention is to simplify the device.

The goal is achieved by the fact that a device for monitoring the technical condition of objects, containing the number of monitored parameters of N sensors of tolerance control connected by inputs to the device inputs, elements NOT and a decoder connected to the outputs of the indicator board, also contains first and second registers, adder, counter, And element, first and second delay elements, clock generator, differentiating element and OR element, connected by inputs to the outputs of the tolerance control sensors and to the information m inputs of the first register, and the output to the input of the differentiating element connected with the output to the (N + 1) -M information input of the first register and to the input of the first delay element connected to the output of the input of the clock generator and to the installation input of the counter zero connected by a counting input to the shift input of the first register, to the input of the second delay element and to the output of the clock generator, and the discharge outputs to the inputs of the And element connected by the output to the input of the Stop of the clock generator and with the enabling input of the second D the gistra connected to the clock input to the output of the second element

delays, and information inputs to the output of the adder connected by the first input to the output of the first register, and the second, third, fourth and five: m inputs - respectively to the first, second, third and fourth outputs of the second register connected by sixteen inputs with the corresponding first inputs of the decoder and with the inputs of the elements HE, tO connected by the outputs to the second inputs of the decoder.

The drawing shows the structural diagram of the device.

The device contains an object 1 cont-15 rol, sensors 2 tolerance control, element RSHI 3, differentiating element 4, first register 5, first element 6 delay, clock generator 7, second element 8 delay, 20 adder 9, second register 10, counter 11 , element I 12, elements NOT 13, decoder 14, the indicator board 15, the first input 16 of the adder, the second 17, the third 18, the fourth-19 and the fifth 20 25 inputs of the adder.

The device works as follows.

In the initial state (corresponds to the OK OK state), the output of the 30 sensors 2 of the tolerance control is affected by the signals O, the output of the logic element OR 3 is the signal O, the generator 7 is in the decelerated state, the first register 5, the second register 10 35 and the counter 11 are in the zero state, at the output of the element I 12 the signal O acts, at the inputs of the decoder 14 connected to the outputs of the second register 10 and the inputs 40 of the elements NOT 13 there is a signal O - and at the inputs of the decoder 14 connected to the outputs of the elements NOT 13 signals 1, as a result that on one of the M outputs of the decoder 45 (M - the number of possible states OK) signal 1 occurs, which affects one of the inputs of the indicator board 15 (transparantnogo type) includes transparency OK OK. 50

If one of the functional elements OK (for example, i-ro) fails, the following occurs. At the outputs of sensors 2 of the tolerance control, a certain combination of signals O and 1 is formed, which is an N-bit binary fault code i-ro of the functional element OK,

which in this case will be transmitted in parallel to the N inputs of the first register 5, represented by itself the N-bit binary code converter.

Since the signals 1, which appeared at the outputs of some sensors 2 of the tolerance control, are transmitted to the inputs of the OR element 3, a single differential occurs at the output of the latter, which, differentiated by element 4 representing the RC circuit, is fed to the N + 1th input of the first register 5 and through the first delay element, which is a LC circuit, is fed to the first input of the generator 7 and the second input of the counter 11. As a result, an N-bit parallel fault code is written in the register, then after turning on the first delay element 6, it wrapped Counter 11 and a pulse generator 7 is started, which consists of an RS flip-flop and a retarded multivibrator.

With the high potential of the single output of the RS flip-flop, the multivibrator is kept in the initial (inhibited) state, begins to generate a sequence of pulses, which are used to shift to the right and read the information in the serial code of the first register 5, while the total number of clock pulses is calculated by the counter 11. When reading the information of the first register 5 is bitwise supplied to the adder 9, which modulo modulates two binary information that arrives simultaneously at its five inputs. The adder 9 is co-located with the second register 10, which is a 16-bit binary code converter (it additionally made tap-offs, mine key elements and, therefore, independent of the permission at the input of the register from the 7th, 9th , 12th, 16th outputs of the parallel code), compresses the N-bit input sequence C.

When summing modulo two information simultaneously arriving at the five inputs of the adder, the latter must implement a switching function of the form

  X, XjXjX fV

VX, X2X, X4XyV X XjjTjX XyV X, X.jX, X, X, X, S,. , x. L, vx,, X, vx, VX, X, X X4XjVX, XjX. V VX XjXjX Xj arguments x, x., L, l, implies signals of the type O or 1, arriving at the inputs 16 - 2 adder 9 from the output of the first register and the 7th, 9th, 12th and 16th outputs the second register 10. In this case, the sequential input of information into the second register 10 with the output of the adder 9 is provided by clock pulses of the generator 7 delayed by a 1% 1m delay element 8 representing the LC circuit for the time of summing in the adder 9 information received from the first register 5 and second register 10 (from outputs 7, 9, 12 and 16). The result of the sequence conversion (the signature is stored in the second register 10. The signature generation process continues for N ticks, i.e. until all the information in the sequential code has been read from the first register 5. With the generation of 7 N-ro pulses simultaneously all K outputs of counter 11 connected to the inputs of the logic element AND 12, signals 1 arise, resulting in signal 1 appearing at the output of the logic element AND 12. This difference is established in the initial (single) state of the RS flip-flop in the gene The generator 7 fails to generate the latter. In addition, this differential enables the output of the parallel code of the second register 10. As a result of this, a parallel 16-bit code is fed to the inputs of the elements NOT 13 and the inputs of the decoder 14, signal 1 appears on one of its outputs. 5 which includes the transparency of the i-th functional element in the indicator board 15. For a small number of monitored parameters, for example 20, the number of decryption inputs is (2) 202 °: 21 "10 info inputs. When compressing a 20-bit code up to 16-bit bottom in the proposed apparatus when the number of information inputs is decoding (neglecting adjacent new elements, indicating little effect on the number of inputs) n 1,05-10 inf. inputs As you can see, even with a small number of controlled parameters OK in the proposed device, the technical implementation of the decryption node of the device is simplified by more than 20 times, thereby simplifying the overall complexity of the known device, and with increasing N the difference in the complexity of the known and proposed device quickly increases, and the complexity of the proposed device increases slightly (only due to the complexity of the element OR 3 and the first register 5). At the same time, the device provides high confidence (99.998%) of decoding the initial N-bit DTC, and the time from the occurrence of a functional element failure to its detection is determined mainly by the shift time of the N-bit code by N bits to the right in the first register, which when operating continuous radio objects, such as radar stations, provides an instantaneous response to failure.

N

Pf vT

eight

eleven

fcP

N

 0

/

13

13

3

lit

W

Claims (1)

DEVICE FOR CONTROL OF PARAMETERS, containing, according to the number of monitored parameters, N sensors. tolerance control, connected by inputs to the inputs of the device, elements NOT and a decoder associated with the outputs of the inputs of the indicator board, characterized in that, in order to simplify the device, it contains the first and second registers, adder, counter, element And, the first and the second delay elements, a clock generator, a differentiating element, and an OR element connected to the inputs of the outputs of the tolerance control sensors and to the information inputs of the first register, and the output to the input of the differentiating element associated with the output from (N + 1) -m inform the input of the first register and with the input of the first delay element connected by the output to the Start Clock input and with the zero setting input of the counter connected by the counting input to the shift input of the first register, to the input of the second delay element and to the output of the clock generator, and by the discharge outputs to the inputs of the element And, connected by the output to the stop input of the clock generator and with the enable input of the second register, connected by the clock input to the output of the second delay element, and the information input to the output of the su a matrator connected by the first input to the output of the first register, and the second, third, fourth, and fifth inputs, respectively, with the first, second, third, and fourth outputs of the second register, connected by sixteen fifth inputs with the corresponding first inputs of the decoder and with the inputs of the ephement NOT connected by the outputs to the second inputs of the decoder.