SU1164909A1 - Synchronizing device - Google Patents

Abstract

A SYNCHRONIZATION DEVICE containing the first binary counter, to the 5R input of which the first output of the second binary counter is connected via the first AND element, and the output of the first binary counter is an output of the device and connected to the C input of a clock trigger, the D input of which is combined with the first input of the second element I is the input of pulses of frame desynchronization, and the inverse output of a clocked trigger is connected to the second input of the second element I, as well as the third element I, and the C input of the first double counter is the tc input of the reference signal, which is the fact that, in order to improve noise immunity and reduce the time to synchronization, the C input of the first binary counter is combined with the direct input of the third And element whose output is connected to the C input of the second binary counter, KSR - the input of which is connected to the output of the second element And, the third input of which is combined with the inverse input of the third element AND and connected to the second output of the second binary meter, which is connected to the second and third inputs of the first element AND, respectively. etstvennoO input and inverted output clocked latch. o: 4:; a. with Oh with

Description

The invention relates to communications, in particular to television, and is intended to synchronize, for example, a frame or line scan of a television receiver. The purpose of the invention is to increase the noise immunity and reduce the time taken to synchronize. Figure 1 shows the structural electrical circuit of the synchronization device; FIGS. 2-4 are timing diagrams explaining his work. The synchronization device contains the first binary counter 1, the first element And 2, clocked trigger 3, the second binary counter 4, the second and third elements And 5 and 6. The synchronization device works as follows. The first input of the synchronization device is supplied with the reference signal of the double frequency pulses, to the second input — the frame synchronization pulses separated from the television signal (FIGS. 2-4 a), the counting ratio of the first binary counter 1, the potential 1 is developed at the first output of the second binary counter 4 at the expense, at the second output - potential 1 at the expense. At the output of the first binary counter 1, as a result of the delePI of the reference frequency, when it returns to the initial state, the pulses with the frequency of the following half-frames (Figures 2–4 b) enter the output of the device and the C input of a clockwise trigger 3. Output The third element, I. 6, is connected to the C-input of the second binary counter 4, the first output of which is with the count. Potential 1 (Figures 2–4 g) arrives at the first input of the first element I 2, and the second output at the end of the count produces potential 1 (F1P 2–4 d), which arrives at the inverse input of the third element I 6 and the third the input of the second element is And 5. The frame synchronization pulses extracted from the television signal arrive at the second input of the first ale. And 2, to the first input of the second element And 5 and to the D input of the clock trigger trigger 3, the signal from the inverse output of which (Fig.2-4c) is fed to the second input of the second element And 5 and to the third input of the first element And 2, the output which is connected to 11 92 SR-input nerve binary counter, and the output of the second element And 5 is connected to the SR-input of the second binary counter 4.. . If the pulses at the second input (Fig. 2a) and at the output of the device are not synchronous, then .C-and D-inputs of a clocked trigger 3 receive pulses that do not coincide in time, and a potential appears at its inverse output (Fig. 2c) M, arriving at the third input of the first element And 2 and at the second input of the second element And 5. Providing synchronism at the previous time, potential 1 is present at the second output of the second binary counter 4 (fig.2d). With the arrival of the frame synchronization pulse to the second input of the device and in the presence of potential 1 on the second and third inputs of the second element 5, the second binary counter 4 is reset, and at the inverse of the third element 6 there appears a potential O allowing the passage of reference frequency pulses to C - the input of the second binary counter, at the third input of the second element And 5, the potential O prohibits the passage of any subsequent pulses from the second input of the device to the SR input of the second binary counter 4. When entering the C-in one second binary counter 4 627 pulses of the reference frequency from its first output (fig.2g) to the first input of the first element And 2 receives a pulse giving permission to pass from the second input of the device to the SR input of the first binary counter 1 only that impulse at the moment of time, which is distant from the frame synchronization pulse by a time equal to the period of the half-frame with its increase by the duration of one line. This provides a check for the periodicity of the frame synchronization pulse, and also checks for its presence at a time instant that is one line from the leading edge, which ensures a constant phase of the pulses at the device’s progress during the subsequent random lag of the frame synchronization pulses for the duration one and a half lines or one line ahead with respect to their average statistical position. The incoming frame synchronization pulse at the moment of passage passage to the SR input of the first binary counter 1 resets it, thereby setting the new value of the pulse phase at the output of the device (Fig. 26). - The first impulse that occurred at the output of the device at the time of resetting the first binary counter 1 sets the level O at the inverse output of the clocked trigger 3, which prohibits the passage of any impulses to the SR inputs of the first and second binary counters 1 and 4. Entering the C input second binary score-15

The 4 628 pulse sets the level 1 at the inverse input of the third element 6 (fig.2d), thereby prohibiting further. passing the reference frequency pulses to the C input of the second binary counter 4.

In the case of the synchronization of pulses at the output of the device and the second input of the device, the presence of interference pulses and the accidental disappearance of a single frame synchronization pulse, the device works as follows (FIG. 3).

With the synchronization of the frame synchronization pulses, the second input of the device and 1l 1 pulses at the output of the device at the output of the clocked trigger 3 present potential O, blocking the effect of interference pulses on the operation of the device (Fig. 3b). In the initial state, at the second output of the second binary counter 4, potential 1 is present (Fig. 3). In the event of a cadre of the synchronization pulse on the inverse code of a triggered trigger, potential 1 occurs (FIG. 3 a, b) arriving at the first input of the first element And 2 and the second input of the second element And 5. With the arrival at the second input of the device, an interference pulse A second binary counter 4 is reset (fig. 3a); at the inverse of the third element 6 there is a potential O (FIG. 3), allowing the passage of reference frequency pulses to the second binary counter 4 coming on With the next frame synchronization pulse clocked at the inverted output of the flip-flop 3 arises potential O (fig.Zv) prohibiting passage of a signal from the first output of the second binary counter to SR-Entrance pereogo binary counter and znache1

and setting in accordance with this a new value of the phase of the pulses at the output of the device (Fig. 4b).

In the case of using a synchronization device to synchronize a horizontal scan of a television receiver, it is necessary to feed pulses of the reference frequency of a highly efficient generator, such as a quartz frequency, to the first input of the device, the frequency of which is determined by the stability requirements of the horizontal synchronizing pulse, to the second input of the device it is necessary to apply horizontal synchronization pulses, in-line

; from the television signal, changing the counting modules of the first and second double counters 1 and 4 in accordance with the reference frequency of the highly stable generator, the synchronization device operates in a similar way.

The invention can be used for devices where synchronous operation of the device with synchronization pulses is necessary, including for synchronous operation of the horizontal and vertical sweeps of the television-south receiver with synchronization pulses, selected from the television signal, and also allows not changing the phase of the pulses by the device, if the synchronization pulses are randomly lagged or advanced by the synchronization pulses from the irx average position for a certain time interval, ensures a change in the phase of the output pulses at presence of interference pulse on arrival of the second synchronization pulse, counting from the time when the not-in-phase was registered, performs a 094 phase of pulses at the output of the device is not izmenits. In the case of repeated no -, frame synchronization Dashul (Fig. 4) at the inverse output of a clocked trigger 3 and at the third input of the first element And 2, the potential 1 continues to remain (Fig. 4c). With the arrival of a pulse from the first output of the second binary counter 4 (FIG. 4d) to the first input of the first element I 2 and the in-phase arrival of the frame sync pulse to the second input of the first element I 2, the new phase value of the frame synchronization is confirmed

adjustment of the phase of the pulses at the output when the phase of pulses of synchronization changes under the conditions of the presence of pulses

interference only by those pulses, the period of which is followed by the Rave, and the period of the synchronization pulses.

FIG. 2

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Claims (1)

A SYNCHRONIZATION DEVICE containing a first binary counter, to the 5R input of which the first output of the second binary counter is connected via the first AND element, and the output of the first binary counter is the output of the device and connected to the C-input of a clocked trigger, the D-input of which is combined with the first input the second element And is the input of the frame synchronization pulses, and the inverse output of the clocked trigger is connected to the second input of the second element And, as well as the third element And, ·, and the C input of the first binary counter is the reference signal, which means that, in order to increase noise immunity and reduce the synchronization time, the C input of the first binary counter is combined with the direct input of the third AND element, the output of which is connected to the C input of the second binary counter, k5R-bxo the output of the second element And, the third input of which is combined with the inverse input of the third element And and connected to the second output of the second binary counter, connected to the second and third inputs of the first element And respectively connected D-input and the inverse output of the clocked trigger.