SU1298952A1 - Synchronizing device - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to increase the noise immunity while reducing the synchronization time. The device contains two counters 1 and 4, seven ELs 2, 5, 6, 8, 9, 11 and 12, D-flip-flop 3, zl-t OR 7 and two RS-flip-flops 10 and 13. The goal is reached by introducing zl-ti OR 7, elec- tives AND 8, 9, 11, and 12, and RS flip-flops 10 and 13, which are used to analyze the duration of the clock pulses input to the device. 4 il. Bo / jfffd sl o with OO y SP yu

Description

The invention relates to television technology and can be used in the synchronization systems of horizontal and vertical scanning of receiving television equipment,

The purpose of the invention is to increase the noise immunity while reducing the time to synchronization.

FIG. Figure 1 shows the structure of the synchronization circuit; in fig. 2–4 are temporary diagrams that show how the device operates in various modes.

The synchronization device contains the first counter 1, the first element AND 2 D-flip-flop 3, the second counter 4, the second 5 and third 6 And elements, the OR 7 element, the fourth 8 and Fifth 9 And elements, the first RS-trigger 10, the sixth 11 and the seventh 12 elements And, the second RS-trigger 13,

The synchronization device operates as follows.

Suppose that the device works in the system of personnel synchronization of the TV. In this case, the input signal of the reference frequency is pulsed with a double line frequency of 2f, and the sync pulse input — frame sync pulses (XI), extracted from the full television signal. The counting ratio of the first counter 1 in this case is equal to .625, and the level of the logical unit is formed at the outputs of the second counter 4 under the following conditions:

on ijepBOM output. - after counting 627 pulses;

on the second output - after 7 pulses;

at the third exit - after 5 impulses;

at the fourth exit - after 628 pulses.

At the output of the first counter 1, as a result of dividing the reference frequency, when counter 1 transitions to the initial state, pulses with the same half-frames are received, which enter the output of the device and the clock inputs of the D-flip-flop 3, If the pulses at the output of the device are in phase with XIs applied to the second input of the device, then on the inverse output of the D-flip-flop 3 there is a logical zero level, which is fed to the second input of the element And 2 and prohibits the passage

five

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0

five

Q

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five

pulses to the installation input of the counter 1; this prevents the passage of interference pulses to the output of the device.

If the pulses at the output of the device are not in phase with XI, or if there is an accidental disappearance of XI (Fig. 2a, 3a, 4a, 2b, 3b, 4b), then the clock and information inputs of the D-flip-flop 3 receive impulses that do not coincide in time , and at the inverse output of D-flip-flop 3 a potential of a logical unit is formed (Fig. 2c, 3c, 4c). This signal arrives at the second input of the element AND 2 and at the third input of the element AND 6. If synchronism is present at the previous time, the potential of logical zero, is present at the first and second inputs of the element OR 7 and at the fourth output of the second counter 4 - the level of logical unity 1 (Fig. 2d, 3d, 4d) 5 which goes to the third input of the element OR 7.

With the arrival at the second input of an XI pulse device (Fig. 2) or an interference pulse (Fig. 3.4) and in the presence of a logical unit potential on the first and third inputs of element And 6, the second counter 4 is reset, while its fourth output forms potential of logical zero (fig, 2d, 3d, 4d), which sets the potential of logical zero at the output of the SHSh 7 element and at the inverse input of the AND 5 element, permitting the passage of the reference frequency pulses from the first input of the device to the clock input of the counter 4 (Fig. 2e , 3e, 4e), as well as prohibiting the passage of l -singular subsequent pulses of the second input device for adjusting the counter input 4 via the AND gate 6.

If the pulse arriving at the second input of the device and resetting the counter 4 to the initial state is an XI pulse, then according to GOST, its duration is equal to 2.5 periods of the horizontal frequency or 5 periods of pulses of the double horizontal frequency. Therefore, when the counter enters the clock input 4 five pulses of the reference frequency, at its third output is the potential of a logical unit NIC61 (Fig.2zh, 3zh, 4zh), which goes to the direct input of the And 8 element, the inverse input of which still has the potential of the logical unit due to XI and the second input

devices. As a result, at the output of the element AND 8 connected to the first input of the element OR 7, the potential of a logical zero remains unchanged, which does not affect the further operation of the device.

Upon receipt of seven reference pulses at the clock input of the counter 4 at the second output of the counter 4 fg, the potential of the logical unit is formed (Fig. 2h), which arrives at the second input of the And 9 element, the first input of which already has the potential jf zero by that time XI is already finished. As a result, at the output of the element And 9 the potential of the logical zero remains unchanged and does not affect the further operation of the device. Counter 4 continues to count the pulses of the reference frequency. After the 627th impulse of the reference frequency arrives at its clock input, a pulse is formed at its first output (Fig. 2d, 3d, 4d), post C, (Fig. 3c, 4c), caused by a non-injecting third input element And 2

The 628th reference frequency pulse sets the logical unity level at the fourth output of counter 4 (FIG. 2d) which through the ISH 7 element enters the inverse input of the AND 5 element, thereby prohibiting further passage of the reference frequency pulses to the analog input of counter 4 (FIG , 2e).

Thus, the device went into synchronism, and its further operation proceeds in the same way as described for the case of synphasic pulses at the output of the device and XI.

The operation of the device in the case when, in the period of non-phase impulses at the output of the device and XI pulses, the second input of the device receives an interference pulse with a duration different from that of the XI, is illustrated by time diagrams (Fig. 3 and 4).

In this case, as in the case described, the inverse output of D-flip-flop 3 has the potential of a logical unit

phase impulses at the output of the device and XI. This level arrives at the third input of the AND 6 element and at the second input of the AND 2 element, and at the fourth output of the counter 4 there is a potential of a logical unit (FIG. 3d, 4e), due to synchronization at the previous moment of time that enters through the element OR 7 on the first input element I 6.

and dacia, the permission to pass from the second input of the device to the installation input of counter 1 only that and fflylyca, which came at a time that is separated from the XI pulse by a time equal to the period of the half-frame with its duration increasing by one line, which provides a check for the frequency of the pulse XI, as well as checking its presence at the moment of time, lagging behind the leading edge for a duration equal to one line, which ensures a constant phase of pulses at the output of the device during the subsequent random XI lagging elnost half lines or advanced by one row weeks long relative to their average position .Po- stepped passage at the time resolution for adjusting input of the counter 1 CSI pulse resets it, thus setting the new value of phase pulses on the output device (26). The first pulse, which appeared at the output of the device at the moment of resetting the counter 1, sets the level of logical zero on the inverse

the output of the D-flip-flop 3 (Fig. 2c), the prohibitions. and reset the counter 4, less the passage of any pulses to the installation inputs of the first 1 and 4 second counters. Received on the clock input of the SECOND counter. four.

c, (figv, 4b), due to non-sync

The 628 th pulse of the reference frequency establishes the level of logic unit at the fourth output of counter 4 (FIG. 2d) which through the ISh 7 element arrives at the inverse input of the And 5 element, thereby prohibiting further passage of the pulses of the reference frequency to the analog input of counter 4 (FIG. 2e).

Thus, the device went into synchronism, and its further operation is similar to that described for the case of the synphasicity of the pulses at the output of the device and the XI.

The operation of the device in the case when, in the period of non-phase impulses at the output of the device and XI pulses, the second input of the device receives an interference pulse with a duration different from that of the XI, is illustrated by time diagrams (Figs. 3 and 4).

In this case, as in the above, the inverse output of D-flip-flop 3 contains the potential of a logical unit

c, (figv, 4b), due to non-sync

phase impulses at the output of the device and XI. This level arrives at the third input of the element And 6 and at the second input of the element And 2, and at the fourth output of the counter 4 there is a potential of a logical unit (fig. 3d, 4e) due to synchronization at the previous moment of time, which comes through the element OR 7 at the first input element and 6.

The impulse of interference arriving at the second input of the device enters the second input of element 6, and in the presence of the potential of the logical unit on the first and third inputs of this element resets counter 4, resulting in its fourth output (fig.3d, 4d), at the output of the element OR 7 and at the inverse input of the element AND 5 there appears a potential of a logical zero prohibiting the passage of any subsequent pulses from the second input of the device to the installation input of counter 4, as well as allowing the passage of reference frequency pulses to the clock input of the account snip 4 (3e, 4e). If the duration of the impulse of the interference received at the second input is more than the duration of the XI, then by the time the potential of the logical unit appears, the third output of counter 4 (after its arrival at

a clock input of five reference frequency pulses (Fig. 4h) arriving at the direct input of an AND 8 element, at the inverse input of this element will already have a potential of zero logic (Fig. 4g), as a result of which the output of the And 8 element will cause a logical units (fig.4i), which, through the element 7, enters the inverse input of element 5, prohibits the passage of reference frequency pulses to the clock input of counter 4 (fig.4e), and the first input of element 6, thereby permitting any following impulses from the second input of the device to the installation th input of the counter 4,

Thus, the device is ready for analyzing subsequent pulses arriving at its second input.

The next impulse arriving at the second input of the device arrives at the second input of element 6 and resets counter 4, and the potential of logical zero at the first input of element 0 appears at the third output of counter 4. And 6, prohibiting the passage of any other subsequent pulses from the second input of the device to the installation input of the counter 4, and also sets the potential of the logical zero at the inverse input of the element I 5, thereby allowing the passage of the reference-frequency pulses counter input assembly 4. Next, the operation is repeated device as described above for the not-in-phase pulses output device and CSI pulses

If the duration of the interfering pulse arriving at the second input of the device and dropping counter 4 is longer than the length of the XI (Fig. 3), then by the time the potential of the logical unit appears at the second output of counter 4 and at the second input of the And 9 element (after it arrives at the clock input of seven pulses of the oyor frequency), the potential of the logical unit will still be present at the first input of the element And 9 (caused by the interference noise at the second input of the device (Fig. 3). As a result, the potential of the logical unit inits, arriving at the R-input of the RS flip-flop 10 and setting on its inverse

output potential of a logical unit. The specified potential of the logical unit is fed to the direct input of the element 12 and through the element OR 7 to the inverse input of the element 5, prohibiting further passage of the reference frequency pulses to the clock input of the counter 4 (fig. Ze) and to the first input of the element 6 , thereby resetting counter 4 to its original state.

After the end of the impulse interference action, the logical element zero level arrives at the inverted input of the And 12 element, as a result of which the potential of the logical unit, which enters the R input of the RS flip-flop 13, is formed at the output of this element, and the potential of the logical unit at its inverse output arriving at the second input element And 11.

Thus, the device is ready for the analysis of subsequent pulses arriving at its second input.

The next pulse arriving at the second input of the device arrives at the first input of the element 11, and since the potential of the logical unit is present at its second input, the potential of the logical unit is formed at the output of the element 11 and enters the S-input of the RS flip-flop 10 and sets at its inverse output the potential of a logical zero, which arrives at the inverse input of the element And 5 thereby resolving the passage of the reference frequency pulses to the clock input of the counter 4 (FIGS. 3i, 3e) and also to the first input of the element 6, thereby prohibiting ohozhdenie subsequent pulses of the second input device for adjusting input of the counter 4. With the direct output RS-flip-flop 10 logic one potential is supplied to S-input of RS-flip-flop 13 and sets it to the initial state.

Further operation of the device is repeated as described for the case of non-phase pulses on the device code and X-ray pulses,

Thus, by analyzing the duration of the pulses arriving at the input of the clock pulses, the proposed device allows to increase the noise immunity while reducing the time to synchronization.

Claims (1)

Invention Formula A synchronization device containing the first counter, the output of which is the output of the device and is connected to the clock input of the D-flip-flop, the clock input is the input of the reference frequency signal, and the setup input is connected to the output of the first And element, the first input of which is connected to the information input D- trigger and is the input of clock pulses, the second input is connected to the inverse output of the D-flip-flop, and the third input is connected to the first output of the second counter, the clock input of which is connected to the output of the second element And, the direct input to The first is connected to the clock input of the first counter, and the inverse input is connected to the first input of the third element I, the second and third inputs of which are connected respectively to the information input and the inverse output of the D-flip-flop, and the output is connected to the installation input of the second counter differing in so that, in order to improve noise immunity while reducing the time of entry 0 five 0 five the element OR, the fourth, the fifth, the sixth and the seventh elements are entered into synchronization. And, the first and second K5-triI1-gers, while the inverse inputs of the fourth and seventh elements And And. The first inputs of the fifth and sixth elements And are connected to the second the input of the third element And, the first input of which is connected to the output of the OR element, the first input of which is connected to the output of the fourth element And, and the second input is connected to the direct input of the seventh element And and to the inverse output of the first RS flip-flop, the direct output of which is connected to S-input second RS-flip-flop, K-input which is connected to the output of the seventh element And, and the inverse output to the second input of the sixth element And, the output of which is connected to the S-input of the first RS-flip-flop, the R-input of which is connected to the output of the fifth element And, and the second, third and fourth outputs the second counter is connected respectively to the second input of the fifth element AND, to the direct input of the fourth element AND, and to the third input of the element OR. f mcpl g e Well I I H R e. p p 1-1 I I 11g Z S in Well g and. Editor A. Shandor (pfi. Compiled by L. Stasenko Tehred A. Kravchuk Order 901/61 Circulation 639. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 I R e. Corrector I. Muska