SU1156146A1 - Storage with self-check - Google Patents

Abstract

A STORAGE DEVICE WITH AUTONOMOUS CONTROL that contains a data collector, an address signal generator, whose inputs are device address inputs, and outputs are connected to data accumulator inputs, a digital signal generator, one of the inputs and outputs of which are information inputs. and the outputs of the device, the decoder, the inputs of which are one of the control inputs of the device, the trigger, the first element AND, the control unit, characterized in that, in order to increase the reliability of the device, He introduced the second and third AND gates, OR gate, OR-NO element, comparing the blocks, switches, registers, control codes generator, a display unit. the driver of the clock pulses and the driver of the control signals, the input of which is connected to the first input of the driver of the clock pulses, and the first output is connected to the inverse input of the trigger, the forward of which is connected to the second input of the driver of the clock pulses, the outputs of which are connected to the inputs from the first to the fourth block of the clock pulse .. the fifth and sixth inputs of which are connected respectively to the output of the second b,

Description

the inputs of which are connected to other outputs of the second switch, the seventh output of the control unit is connected to the control input of the second comparison unit, the outputs from the eighth to the tenth are connected to the control inputs of the third register, and the eleventh output. Connected to the first input of the first register, the second input , the third input of the second register and the direct input of the trigger are connected to the second output of the control signal generator, the twelfth output of the control unit is connected to the first control input of the first switch, the second pack The main input of which is connected to the output of the third element AND, the first input of which is connected to the thirteenth output of the control unit, and the second input is combined with the second inputs of the second element AND, the OR-NOT element, the second input of the second element AND, and the input of the control signal generator other control inputs of the device.

The invention relates to computing, in particular, to storage devices, and can be applied in microprocessor control systems.

 A self-memory memory device, in which the KOHjpcxHbHbix method of counting is used to control the operation of the device, in which the contents of each of the memory cells alternately double-fold with a completely single word i.

A disadvantage of this device is low reliability.

The most popular is a locking self-monitoring device containing a local control unit, a processor, a microinstruction register, the first and second pavers that are connected to the corresponding inputs of the RAM, which are permanently stored, and the decoder signals The control unit, the clock pulse generator, the generator control trigger and the AND element, the address buses and the RAM data buses, are connected to the bus driver, and the first and second control inputs Pitel pyhodou connected to, registers of | 5a microinstructions N1INNYH formers other terminals are connected to respective inputs and outputs npoiieccopa 2.

The disadvantage of the prototype is low reliability, since there is no monitoring provided during the operation of the device and it is necessary to periodically disconnect the drive in order to carry out preventive functional monitoring.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved by the fact that a memory device with autonomous control, containing a data collector, an address signal generator, whose inputs are the device's address inputs, and outputs connected to

the data accumulator inputs, the numerical signal generator, one of the inputs and outputs of which are information inputs and outputs of the device, the decoder whose inputs are one of the control inputs of the device, the trigger, the first And element and the control unit, the second and third And elements are entered , element OR, element OR - NOT, comparison blocks, switches, registers, driver of control codes, display unit, driver of clock pulses and driver of control signals, the input of which is connected to the first input of the phono tors, clock, and a first output connected to the inverted input of the flip-flop, straight ko5 torogo output connected to the second input for.mirovatel clock, outputs of which are connected to inputs of the first to fourth control unit, fifth and sixth inputs which are respectively connected to the output

0 of the first comparison unit and the first input of the OR-NOT circuit and to the output of the second comparison unit, one of the inputs of which and one of the inputs of the first switch are connected to the outputs of the control code generator, the inputs of which are connected to the outputs of the first register and the group of inputs of the control unit , the first and second outputs of which are connected respectively to the first inputs of the first and second elements AND, and the third and fourth outputs are connected respectively to the first input of the second register and to the second input of the second register and the control at the input of the first comparison unit, one of the inputs of which is connected to one of the outputs of the second register and the inputs of the display unit, the control input of which is connected to the fifth output of the control unit, the sixth output of which is connected to the first control inputs of the second switch, the second control the input of which is connected to the output of the first block

0 comparison, the other inputs of which are connected to other outputs of the second register and

address inputs of the data accumulator, the first control input of which is connected to the output of the nerve element AND, the second input of which is connected to the output of the OR element, the first and second inputs of which are connected respectively to the output of the OR-NOT element and to the output of the decoder and the seventh input of the control unit, the eighth the input of which is connected to the output of the second element And and the second control input of the data accumulator, the information inputs and outputs of which are connected respectively to the outputs of the first switch, with one of the inputs of the second switch Ator, other inputs of the second unit of comparison and the inputs of the third register, the outputs of which are connected to other inputs of the second switch, and the other inputs of the first room :. - ;; the torus is connected respectively to one of the outputs of the second switch and to the other and to the outputs of the numeric ciii pa / yv generator, the other inputs of which are connected to the other outputs of the second switch, the seventh output of the control unit is connected to the control input of the second comparison unit, the eighth through the tenth outputs are connected to the control inputs of the third register, and the eleventh output is connected to the first input of the first register, the second input of which, the third input of the second register, and the direct trigger input are connected to the second output of the form control signal terminal, the twelfth output of the control unit is connected to the first control input of the first switch, the second control input of which is connected to the output of the third element And, the first input of which is connected to the thirteenth output of the control unit, and the second input is combined with the second inputs of the second element And The OR-NOT element, the second input of the second element AND, and the input of the driver of the control signals are other control inputs of the device.

FIG. 1 is a functional diagram of the proposed device: FIG. 2 is a functional diagram of the most preferred embodiment of the control unit.

The proposed device contains (FIG. D) shaper 1 address signals with inputs 2, shaper 3 numeric signals from inputs 4 and outputs rk 5, data storage 6 with information first 4 inputs and outputs 7, a decoder 8, control inputs 9 -eleven.

The device also contains the element OR 12, the elements AND 13-15 from the first to the third, the control block 16, the driver 17 clock pulses, the trigger 18, the driver 19 controls the signals, the element OR NOT 20, the first 21 and the second 22 registers, the first block 23 comparison, block 24 of the display, the second block 25 sg), the third register 26, the first 27 and second 28 switches, and the driver 29 of the control codes.

The device contains outputs 30-42 and inputs 43j-43 /, 44-47 of control unit 16.

The control unit 16 contains a decoder 48, elements NOT 49-55, elements OR 56-61, elements AND 62-66, elements AND-HE 67 and 68, element OR-NOT 69, trigger 70, load element 71 and key 72.

The formers 1 and 3 can be made on the basis of the K589AP16 microcircuits.

As a driver of control codes 29, a permanent drive can be used.

The proposed device operates as follows.

In the initial state, the toggle switch in the driver 19 (Fig. 1) is nahs, nts in the “Off” position and clock pulses with

0 input 11 is fed to the input of the trigger 18, the zero reset inputs of registers 21 and 22. The part of the device that provides the functional control of the drive 6 is turned off and the ycTpoiicTBO works in the same way as the prototype.

When reading, the inversion signal (zero) comes from inputs 9 to the input of the element And 13 and then to the entrance of the accession accumulator 6. To the input of the element 11, a signal is received (unit) and then to the input of the accumulator 6. The signal "The input to the elec Meta AND - NOT 67 (Fig. 2). As a result, at its output 35 will be one. Investigator. switch 28 will be opened (fig. 1). The read information from accumulator 6 through switch 28 is fed through shaper 3 to outputs 5, since at the output of block 2, a mismatch signal (zero), which opens the first group of inputs to the switch 28 for

passing information read from drive 6

When writing to the input of the element And 13 and VHO.L, drive 6, a reverse signal is received. The input element And 14, the input element And 15 and the input of the accumulator 6 receives the write signal (zero), which opens the switch 27 through the element 15 and the information from the inputs 4 of the forward link 3 enters the record in the accumulator 6.

After pressing key 72 in block 16 and

0 after the toggle switch in block 19 is turned on, the trigger 18 is switched to a single-lane state and the clock signals start to start: the driver 17, in which a sequence is generated with the arrival of each pulse

signals, which is iiocTyriaeT at the inputs from block 16. Moreover, this sequence of signals is generated in that part of the clock cycle, when the accumulator is loaded with 6 kilowatts of power. Thus, there is a pause when accessing the biv drive. During this pause, the operation of the device is monitored.

Functioning control starts from zero address (register 22 is reset).

The control cycle of each word from accumulator 6 consists of six cycles, each of which is performed during a pause between the two devices to the device.

The first clock cycle consists in rewriting the monitored controlled cell on the liHTe .ii- 6 into the register 26. From block 16 to the input, m -; - mg; gga 1-1 13, a reverse signal is received, to the input h.:; Measure and 14 - the signal. chig;, 1vapi. From output 33 of block 16 to the input of poi Istra 22 receives a zero signal, which gives the address of the controlled cell from register 22 to the address inputs of accumulator 6. Register 26 is enabled to receive information. After a delay, it is necessary for me to retrieve information from accumulator 6, the nose is written to register 26. At the end of the clock cycle, one is added to register 21.

The second cycle consists in recording instead of the read control code, for example, all units. Under the action of the code coming from register 2 into block 16, the latter organizes the write mode to drive 6. For this, through the AND 13 element, a reversal signal is given, and through the AND 14 element, a recording signal. The switch 27 opens and passes the signal from the accumulator 29, from which units are received. A unit is added to register 21.

The third clock is to read the control code from accumulator 6 and compare it with that recorded in block 25. Switch 28 and register 26 are not included. A match (mismatch) signal is received at block 16. If there is no equality, a control signal is generated by block 24 and the operator can determine the fault address. A unit is added to register 21.

The fourth clock cycle is to write to the monitored cell of another control code, for example, all zeros. This clock is similar to the second clock, but the output is a register; –21 is another code, which determines the output from block 29 of another code. At the end of the cycle, a unit is added to register 21.

The fifth cycle is to read from the accumulator 6 of the control code and compare it with the recordable one, similarly to the third

tact. At the end, one is added: 1a to the register 21.

The sixth clock cycle is to write to the drive 6 the source information from periicT5 pa 26. At the end of the clock one unit is added to registers 21 and 22 (KOTO) iiFe, -ipop the next address is next :,

In the pro-mix between these tags, it is possible to refer to the drive 6. Pr; -:

In this case, two cases are possible: the call occurs to the uncontrolled cell and the call occurs to the controlled cell. In the first case, the operation occurs as in the case when the toggle switch in the driver 19 is in the "Off" position.

5 because in the pauses block 16 provides the same potential for the inversion (of the initial state).

In the case of a monitored cell (this is determined by block 23), the information is recorded or read into a device 26, and the record occurs through a code; mountains 28 to register 26, and from it through the comm; :: t () p 27 to the inputs of the accumulator 6.. To prevent (writing information into a coping cell, use the

5 OR l 2, Il-NOT 20.

It should be noted that the use of the element OR-NE 20 is not the only possible solution to the problem. We can limit the access to the controlled cell. A more stringent limitation is the use of the element NOT instead of the element OR-HE 20, and the element's input does NOT need to be connected to the output of block 23. In this case, it is prohibited to access the monitored cell not only

5 in write mode, but also in read mode.

An even simpler solution is to use a comparison unit with an inverse output. For this, it is enough to use the NAND element (not shown) instead of the AND element at the output of block 23. This will require a change in the inputs of the second switch 28, namely, the first and second informational inputs need to be swapped. In addition, it is necessary to exclude element 50 in block 16 (Fig. 2).

Feasibility study

The proposed device is

higher reliability compared to the prototype.

Claims (1)

A MEMORY DEVICE WITH AUTONOMOUS CONTROL, containing a data storage device, an address signal generator, the inputs of which are address inputs of the device, and the outputs are connected to the address inputs of a data storage device, a digital signal generator, one of the inputs and outputs of which are information inputs and outputs of the device, a decoder, the inputs of which are one of the control inputs of the device, a trigger, a first AND element, a control unit, characterized in that, in order to increase the reliability of the device, into it the second and third AND elements, the OR element, the OR-HE element, comparison blocks, switches, registers, control code generator, display unit, clock generator and control signal generator, whose input is connected to the first input of the clock generator and the first output is connected to an inverse trigger input, the direct output of which is connected to the second input of the clock generator, the outputs of which are connected to the inputs from the first to the fourth control unit, the fifth and sixth inputs of which are connected to corresponding to the output of the first comparison flare and the first} · input of the OR element NOT and the output of the second comparison unit, one of the inputs of which and one of the inputs of the first switch are connected to the outputs of the control code generator, the inputs of which are connected to the outputs of the first register and the group of inputs of the control unit , the first and second outputs of which are connected respectively to the first inputs of the first and second elegieng And, and the third and fourth outputs are connected respectively to the first input of the second register and to the second input of the second reg Istra and the control input of the first comparison unit, one of the inputs of which is connected to one of the second register and inputs of the display unit, the sculpting input of which is connected to the fifth output of the control unit, the sixth output of which is connected to the first control inputs of the second switch, the second control the input of which is connected to the output of the first comparison unit, the other inputs of which are connected to other outputs of the second register and the address inputs of the data storage device, the first control input of which is connected to the output of the first th AND element, the second input of which is connected to the output of the OR element. the first and second inputs of which are connected respectively to the output of the OR — NOT element and to the output of the decoder and the seventh input of the control unit, the eighth input of which is connected to the output of the second element And and the second control input of the data storage device, the information inputs and outputs of which are connected respectively to the outputs of the first switch , with one of the inputs of the second switch, other inputs of the second comparison unit and inputs of the third register. the outputs of which are connected to other inputs of the second switch, the other inputs of the first switch being connected respectively from the outputs of the second switch and to the other outputs of the numerical signal former, the inputs of which are connected to other outputs of the second switch, the seventh output of the control unit is connected to the control input of the second block comparison, the outputs from the eighth to tenth are connected to the control inputs of the third register, and the eleventh output is connected to the first input of the first register, the second input to the third input of the second register and the direct input of the trigger are connected to the second output of the control signal generator, the twelfth output of the control unit is connected to the first control input of the first switch, the second control input of which is connected to the output of the third element And, the first input of which is connected to the thirteenth output of the block control, and the second input is combined with the second inputs of the second AND element, the OR element — NOT, the second input of the second AND element and the input of the control signal generator are other their inputs.