KR100348218B1 - Dual Data Rate Synchronous Memory Devices - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a dual data rate synchronous memory device capable of reducing chip area by using a global data bus capable of data transfer in both directions in common for read and write operations. To this end, the present invention, an external input and output block that is responsible for input / output of data, a memory cell block in which memory cells are collected, and write data from the external input / output block to a memory cell or write data from a memory cell to the external input / output block. By having an internal I / O block for sending data and a single global data bus which is installed between the external I / O block and the internal I / O block for data transmission in both directions, the number of data bus lines is reduced and the chip area is greatly reduced. .

Description

Dual Data Rate Synchronous Memory Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual data rate synchronous memory device, and more particularly, to a dual data rate synchronous memory device in which data buses are bidirectionally used in a double data rate synchronous memory device. It is about.

In a system for exchanging data with a memory device, a general synchronous memory device is a method of receiving only one data (reading from a memory device) or writing to a memory device for one clock period.

As shown in FIG. 1, the general synchronous memory device includes an external input / output block 10 connected to a data pin of a memory device and configured to perform input / output, a memory cell block 14 in which memory cells are collected, and a memory. An internal input / output block 12 for writing data to or reading data from a cell may be configured, and one external input / output block 10 may be connected to a plurality of internal input / output blocks 12.

The external input / output block 10 and one or more internal input / output blocks 12 are interconnected by a read-only data bus 16a and a write-only data bus 16b.

Referring to the signal waveform diagram of FIG. 2 for the " following read / write " operation in the conventional synchronous memory device configured as described above, the time for which data is loaded on the data bus 16a in the read operation is determined by the memory cell block ( 14) and through the internal I / O block 12. In contrast, the time when data is loaded on the data bus 16b in the write operation is when the data is to be transferred from the external input / output block 10 to the internal input / output block 12 before the memory cell block 14 is accessed.

Here, the data is loaded on the data buses 16a and 16b when the " following read / write " operation is assumed assuming that the time for accessing the memory cell block 14 during the read operation or the write operation is constant. The interval of time becomes smaller than one clock period.

This is a factor that limits the maximum frequency of operation of a typical synchronous memory device.

In order to solve this problem, a dual data rate synchronous memory device has been introduced to increase the data exchange rate per hour with a memory device. Unlike the conventional synchronous memory device, a dual data rate synchronous memory device has been used twice during one clock cycle. Data input and output is possible.

In other words, the general dual data rate synchronous memory device adopts the data bus structure of a conventional synchronous memory device having two one-way data buses. As shown in FIG. This is different from the synchronous memory device.

And since the write command is at least two clocks away from the cycle in which the read operation is performed, there is no possibility that the read data and the write data meet on the data bus.

However, in the conventional dual data rate synchronous memory device, the amount of data exchange per hour between the internal I / O block and the external I / O block must be increased in order to increase the data exchange rate.

One solution to this problem is to double the data exchange rate, or frequency, and to double the amount of data exchanged at one time.

When the first method is selected, there is a technical difficulty in doubling the operating frequency, and the second method is technically easy to apply. In order to apply the second method, the data bus of FIG. You need to increase the width.

In other words, the number of signals must be doubled. This is a technically very easy method to achieve, but it is a disadvantage compared to conventional synchronous memory devices because it must be solved by increasing the chip area.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and a dual data rate synchronous memory device capable of reducing chip area by using a global data bus capable of data transfer in both directions in common for read and write operations. The purpose is to provide.

In order to achieve the above object, a dual data rate synchronous memory device according to an embodiment of the present invention comprises a memory cell block consisting of a plurality of memory cells; An external input / output block for inputting data internally or outputting the data externally; An internal input / output block for writing data from the external input / output block to a memory cell in the memory cell block or transferring data from the memory cell to the external input / output block; A single global data bus disposed between the external input / output block and the internal input / output block to transfer data in both directions during a read and write operation; And a self precharge block for automatically precharging the global data bus without any external commands during the read and write operations, wherein the single global data bus is automatically with the self precharge block without external commands when writing data. Transmits a data input signal to the memory cell block in a precharged state, and transmits a read data signal to the external input / output block in a state of being automatically precharged by the self precharge block without an external command when reading data. It is characterized by.

1 is a block diagram of a general synchronous memory device;

2 is a signal waveform diagram for a " following read / write " operation possible in a typical synchronous memory device;

3 is a signal waveform diagram for a " following read / write " operation possible in a typical dual data rate synchronous memory device;

4 is a block diagram of a dual data rate synchronous memory device according to an embodiment of the present invention;

FIG. 5 is an internal circuit diagram of the dual data rate synchronous memory device shown in FIG. 4.

<Description of the reference numerals for the main parts of the drawings>

10: external I / O block 12: internal I / O block

14: memory cell block 16a: read-only data bus

16b: write-only data bus 18: global data bus

20: Self Precharge Block

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram of a dual data rate synchronous memory device according to an exemplary embodiment of the present invention, in which an external input / output block 10 connected to a data pin (not shown) and responsible for data input / output and a memory cell are assembled. A memory cell block 14, an internal I / O block 12 for writing data from the external I / O block 10 to a memory cell or sending data from a memory cell to the external I / O block 10, the external I / O block A single global data bus 18 provided between the internal I / O block 12 and data transfer in both directions, and a self precharge block for setting an initial level of the global data bus 18 ( 20).

Here, as illustrated in FIG. 5, the external input / output block 10 may include a NAND gate 10a for receiving a data input signal data_in and a write strobe signal write_strobe, and NAND processing from the NAND gate 10a. A buffer 10b for buffering a signal of the switching element, and a switching element 10c connected between the global data bus 18 and the ground voltage Vss and driven on / off by a signal from the buffer 10b; Transistor) and an inverter 10d as a receiver which is connected to the global data bus 18 and the drain of the switching element 10c and receives the data of the memory cell via the global data bus 18 to the outside. .

As illustrated in FIG. 5, the internal input / output block 12 includes a NAND gate 12a for receiving a read data signal read_data and a read strobe signal read_strobe, and a NAND gate, and the global data bus 18. And a switching element 12b (NMOS transistor) connected between the ground voltage Vss and driven on / off by a signal from the NAND gate 12a, and the global data bus 18 and the switching element 12b. And an inverter 12c as a receiver which is connected to the drain of and receives the data from the external input / output block 10 via the global data bus 18 and sends it to a memory cell (not shown).

Meanwhile, as shown in FIG. 5, the self precharge block 20 includes a MOS device 20a (PMOS transistor) connected between the global data bus 18 and the power supply voltage Vcc, and the global data bus 18. And an inverter 20b connected to one end of the MOS element 20a, and a delay element 20c for delaying the output signal of the inverter 20b by a predetermined time and applying it to the control terminal (gate) of the MOS element 20a. ).

Next, an operation of the dual data rate synchronous memory device according to the embodiment of the present invention configured as described above will be described.

When data is to be written to a memory cell existing in the memory cell block 14, data is stored in the order of the external I / O block 10 → global data bus 18 → internal I / O block 12 → memory cell block 14. On the contrary, when the data of the memory cell is to be read, data is output to the outside in the order of the memory cell block 14 → the internal input / output block 12 → the global data bus 18 → the external input / output block 10. .

In other words, when trying to write data to the memory cells existing in the memory cell block 14, the global data bus 18 is first precharged to the high (H) level by the self precharge block 20. The data input signal data_in and the write strobe signal write_strobe are input to the NAND gate 10a in the external I / O block 10 to perform NAND processing, and the switching element 10c is activated by a signal through the buffer 10b. As it is turned on, the global data bus 18 transitions to the low (L) level, and the low level signal loaded on the global data bus 18 goes to a high level through the inverter 12c in the internal input / output block 12. After inversion, the memory cell block 14 is transferred to the memory cell block 14.

On the contrary, when the data of the memory cell is to be read, the read data signal read_data and the global data bus 18 are first precharged to the high (H) level by the self precharge block 20. As the read strobe signal read_strobe is input to the NAND gate 12a in the internal I / O block 12 and NAND processed, and the switching device 12b is turned on by the NAND processed signal, the global data bus 18 is low. The signal is transferred to the (L) level, and the low-level signal loaded on the global data bus 18 is inverted to a high level through the inverter 10d in the external input / output block 10, and then transferred to a data pin (not shown). Is output.

As described above, the signal waveform on the global data bus 18 takes the form of a negative pulse while a write operation of writing data to a memory cell and a read operation of reading data of the memory cell are performed. And the internal input / output blocks 10 and 12 drive the global data bus 18 only at a low level through the switching elements 10c and 12b, and the global data bus 18 is driven by the self precharge block 20. After a period of time (i.e., a time such that the writing and reading operation of data is completed), it is restored to a high level.

According to the present invention as described above, the chip area can be greatly reduced by reducing the number of data bus lines in the dual data rate synchronous memory device.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (5)

A memory cell block consisting of a plurality of memory cells; An external input / output block for inputting data internally or outputting the data externally; An internal input / output block for writing data from the external input / output block to a memory cell in the memory cell block or transferring data from the memory cell to the external input / output block; A single global data bus disposed between the external input / output block and the internal input / output block to transfer the data in both directions during a read and write operation; And A self precharge block which automatically precharges the global data bus without external commands during the read and write operations, The single global data bus transmits a data input signal to the memory cell block in a state of being automatically precharged by the self precharge block without an external command when writing data, and when the data is read, by the self precharge without an external command. A dual data rate synchronous memory device for transmitting read data signals to an external input / output block in a state of being automatically precharged by a charge block. The method of claim 1, The self precharge block, A MOS device connected between the global data bus and a power supply voltage; An inverter connected to one end of the global data bus and the MOS element; And a delay element for delaying an output signal of the inverter by a predetermined time and applying it to the control terminal of the MOS element. The method of claim 2, The MOS device is a dual data rate synchronous memory device, characterized in that consisting of a PMOS transistor. The method of claim 1, The external input output block, A logic element for receiving and logically combining the data input signal and the write strobe signal; A buffer for buffering a signal from the logic element; A switching element connected between the single global data bus and a ground voltage and switched by an output signal from the buffer; And an inverting element connected to a common contact point of the single global data bus and the switching element and receiving and inverting data from the memory cells in the memory cell block through the single global data bus and inverting the data. A dual data rate synchronous memory device. The method of claim 1, The internal input and output block, A logic element configured to receive and logically combine the read data signal and the read strobe signal; A switching element connected between the single global data bus and a ground voltage and switched by an output signal from the logic element; An inverting device connected to the common contact point of the single global data bus and the switching device, and receiving and inverting data from the external input / output block through the single global data bus and inverting the data to the memory cell of the memory cell block Dual data rate synchronous memory device, characterized in that consisting of.