SU1156142A1 - Analog storage - Google Patents

Abstract

ANALOG STORAGE DEVICE containing a storage element on a capacitor, the first amplifier whose input is the device input, the output of the first amplifier is connected to the first key input, the second input of which is connected to the first input of the control unit and the control bus, the first one. The second and third comparators, the outputs of which are connected respectively to the second, third and fourth inputs of the control unit, the output of the control unit is connected to the first input of the switch, the second, third and fourth inputs of which are connected to the first, second and third buses of the reference voltages, respectively. the inputs of the comparators are connected to the inputs of the first amplifier, the second inputs of the comparators are connected respectively to the busses of the reference voltages, the second amplifier, the output of which is the output of the device, characterized by that, in order to simplify the device, in it the key output is connected to the input of the second amplifier and to the first capacitor plate, the second plate of which is connected to the output of the switch. (L

Description

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ipus.f The invention relates to computing, in particular to storage devices, and can be used, for example, in instrumentation for temporal discretization of analog signals. The purpose of the invention is to simplify the device. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - time diagrams that show his work. The proposed device (Fig. 1) contains amplifiers 1 and 2, a switch 3, a storage element on a capacitor 4, a control bus 5, comparators 6, 7 and 8, a control block 9, a switch 10, bus voltages 11, 12 and 13. The values of the reference voltages Ui ... U (Fig. 2a) are selected to lie within the dynamic range of the input signals of the analog storage device. The difference between two adjacent reference voltages is q. The value of q is chosen from the condition cj - where Umax is the dynamic range of the memorized signals; K is the desired rate of increase in speed, + 1 (N is the number of reference voltages). The proposed device operates as follows. At the moment the memory pulse arrives at the control bus 5 (Fig. 26), which determines the moment of storing the input signal level, the key 3 closes and the output signals of the control unit 9 are switched. The input voltage in FIG. 2a compares ".... in amplitude with the reference voltages with the help of Comparators 6, 7 and 8, as a result of which at each time point a combination of signals is detected at the inputs of control unit 9 determined by the amplitude of the input signal. Each combination of signals at the input of control unit 9 corresponds to an output set of logic signals which, in the presence of a memory pulse (Fig. 2b), switch switch 10 so that a reference voltage that corresponds to the comparator that triggered last is connected to the capacitor 4 capacitor plate. E. Closest to the voltage of the signal and smaller than its value (Fig. 2d). The voltage is switched on (Fig. 2d) with a delay, determined by the delays of the control unit 9 and the switch 10. Thus, one plate of the capacitor 4 is applied through a closed key 3 to the input voltage (Fig. 2a) and to the other - reference voltage (Fig. 2d). As a result, the accumulative capacitance 4 is charged to the value of the difference between the reference voltage and the input signal (AUz, diz, fig. 2c). The value at this difference cannot exceed the value ((Fig. 2a). At the end of the memory pulse (Fig. 2b) the device goes into storage mode, the key 3 is opened, the switch 10 of the output of the control unit 9 is disabled (the selected reference remains the voltage of the amplifier 2 is fixed to a voltage equal to the sum of the corresponding reference voltage on one of the buses 11, 12, 13 and the voltage on the capacitor 4 (Fig. 2c). This is the total voltage equal to the voltage of the input signal at the time of the pulse the choice and (Fig. 26) is transmitted to the output by amplifier 2. Thus, in the proposed device, as in the prototype, which is taken as the basic object, in the memory mode, the capacitor 4 is charged to a value not exceeding the difference between the adjacent reference voltages q, but this increases reliability, simplifies the circuit, improves manufacturability and increases accuracy, since fewer switches are used to switch the signal and the error caused by the passage of control key signals to the capacitor 4 is reduced.

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Claims (1)

ANALOGUE REMEMBERING DEVICE containing a storage element on a capacitor, the first amplifier, the input of which is the input of the device, the output of the first amplifier is connected to the first input of the key, the second input of which is connected to the first input of the control unit and to the control bus, the first, second and third comparators, outputs which are connected respectively to the second, third and fourth inputs of the control unit, the output of the control unit is connected to the first input of the switch, the second, third and fourth inputs of which are connected respectively Actually with the first, second, and third reference voltage buses, the first inputs of the comparators are connected to the inputs of the first amplifier, the second inputs of the comparators are connected respectively to the reference voltage buses, the second amplifier, the output of which is the output of the device, characterized in that, in order to simplify the device, the key output is connected to the input of the second amplifier and to the first capacitor lining, the second lining of which is connected to the output of the switch. figure 1 I w / ⁽ ///