SU1488877A1 - Analog storage unit - Google Patents

Description

The invention relates to analog storage devices and can be used in various analog-digital systems, in particular in multifunctional programmable interface devices with digital computers with external sources and receivers of analog signals,

volume · number in programmable analog interfaces of digital computers. The purpose of the invention is to improve the accuracy and enhancement of functionality due to the implementation of various operations of processing and converting analog information. The integration accuracy is improved by eliminating the integration error associated with the presence of the bias voltage of the amplifier amplifier 1 The device allows for the following functions: AZS, extremator, exponential signal generator, linear variable generator, inverting and non-inverting integrator, nonlinear converter of the input signal in the time interval . The device contains an amplifier 1, cumulative elements 2,3, memory block 4, restrictive elements 5,6, key elements 7-12, passive elements 13,14. 1 il.

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The invention relates to analog storage devices and can be used in various ana-logo-digital systems, in particular, in multifunctional programmable interface devices of digital computers with external sources and receivers of analog signals, including programmable analog interfaces of digital computers.

The purpose of the invention is to improve the accuracy and expansion of functionality due to the implementation of various processing operations and the conversion of analog information.

The drawing shows a block diagram of the device.

The device contains an amplifier 1, first 2 and second 3 cumulative elements on capacitors, memory block 4, first 5 th second 6 restrictive * elements on diodes, first 7, second 8, third 9, fourth 10, fifth 11, sixth 12 key elements, the first 13 and second 14 passive elements on resistors, the first 15 and second 16 information inputs of the device.

The device works as follows.

In the initial state, all elements 7-12 are open. In the mode of normal sampling (recording) of the input analog signal, the elements 7 and 8 are closed by applying the corresponding control signals to their control inputs. When switching from the sampling mode to the storage mode, the elements of the 7 th 8 synchronously open. If elements 7 and 8 are made in the form of identical field-effect transistors, and the capacitances of elements 3 and 2 are equal, the switching error is compensated, caused by the transmission of part of the control signal through the parasitic capacitance gate-source (or gate-drain) from the control circuit in the circuit 3 ( i.e., to the non-inverting input of amplifier 1), since simultaneously a signal of the same sign and size is formed at the inverting input of amplifier 1. Since amplifier 1 amplifies only the difference of input signals, a simultaneous voltage change s at its inverting and noninverting inputs at the same value does not change the signal

at the output of the amplifier 1, therefore, at the output of the device.

When the device operates in the signal extremator mode (ie, in the peak detector mode), element 8 and one of the elements 10 or 11 are closed, depending on what the maximum or minimum signal level is written to the device. For example, when recording a maximum, element 10 closes.

The device operates autonomously, while the magnitude of the direct resistance and the direct voltage drop across elements 5 and 6 should be minimal (for 3ϊγγ, for example, diodes such as D311 can be used). At the moment of maximum passage (in the maximum recording mode) of the input signal, element 6 is turned on in the forward direction, and element 3 is charged almost to the maximum voltage of the input signal. When the input voltage drops, element 6 is turned on in the opposite direction, and element 3 retains the memorized maximum voltage value, which can be read from the device output. If it is necessary to stop searching for the maximum, elements 10 and 8 open synchronously. In the case of the execution of elements 10,11 and 8 in the form of identical field-effect transistors, the error is compensated, caused by the transfer of a part of the control signal from the control circuit to the memory circuit of the element 3, as in the case of the usual sampling and storing mode of the analog signal.

To reset the extremator, i. to discharge the element "to zero potential, elements 8 and 12 are closed. Element 3 is discharged through elements 12 and 14, and element 2 is discharged through closed element 8.

In the exponentially-decreasing signal generator mode, elements 8 and 7 are closed and element 3 is charged to the initial voltage from an external voltage source. Element 7 then opens and closes element 12. Element 3 begins to discharge through element 14 along the exponent repeating at the output of the device. As a resistor 14 can use

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entail own resistance of the element 12, for example in the case of the execution of the element 12 in the form of a field-effect transistor.

In the normal integrator mode, the integrated signal is fed to input 16. At the same time, unit 4 continuously operates in the input-signal sampling mode, thereby ensuring its passage to its own output. Elements 12 and 9 are closed, the other key elements are open. Thus, a non-inverting 7 input of amplifier 1 is supplied with a zero potential, element 2 is switched on in the negative feedback circuit of amplifier 1, and element 13 between the output of block 4 and inverting input of amplifier 1 is 13. The time constant of such an integrator is determined by multiplying the element 2 by the sum of the resistances of the elements 9 and 13 in the closed state.

In the generator mode of linearly increasing voltage in the initial state, elements 8 and 12 are closed, and to input 16 some constant voltage is supplied and recorded in block 4 (the value of which determines the rate of change of linearly varying voltage at the output of amplifier 1). When switching to the generation of a linearly varying voltage, element 9 ·· closes

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and element 8 opens, i.e. amplifier 1 is switched to the generator mode (inverting) at its inverting input. To generate a linearly increasing voltage in block 4, it is necessary to record a negative voltage, to generate a linearly decreasing voltage in block 4, a positive voltage is written.

To generate a periodic linearly varying signal with the output voltage returning to zero potential, it is sufficient in the mode of generating a linearly increasing or decreasing signal to periodically close element 8. At the same time, element 2 periodically discharges through closed element 8 to zero, providing repeated linear increase or decrease after element 8 opens. signal output device.

When integrating a signal coming through a closed. Element 7 to the non-inverting input of amplifier 1, element 9 is closed, element 8 is open, i.e. in fact, the voltage difference between the output of unit 4 and input 15 of the device is integrated. When writing in block 4 zero levels and taking into account the inversion of the sign of the integration result, the signal arriving at input 15 is actually integrated without inverting the sign of the result, i.e. This mode corresponds to the non-inverting integrator mode on input 15.

To improve the integration accuracy by eliminating the integration error associated with the presence of the bias voltage of the amplifier 1, the device output is connected to the input 16. In the initial state, block 4 records a compensating voltage equal to the zero bias voltage of the amplifier 1, for which the elements 12 and 8 are closed (other key elements are open). Then the elements 8 and 12 open, and the elements 7 and 9 are closed - the device enters the mode of integrating the signal at the input 15 of the device.

In the process of integrating their integration result, the error associated with the presence of mating zero offset of amplifier 1 is subtracted by supplying the corresponding compensating voltage to the inverting input of the integrator from the output of block 4.

The device can also operate “in the mode of nonlinear conversion of the input voltage to the time interval, defined as the time interval from the start of the integration process until the output voltage of the amplifier 1 is zero. To do this, with closed elements 7 and 8, from input 15 to element 3, the input voltage U is recorded, and in block 4 from input 16, the voltage D _g . Then elements 7 and 8 open, and element 9 closes. Voltage and _v1x at the output of amplifier 1

begins to change according to the law

and _6x (O ⁼ ϊ I (and _r- s,) db + and,

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where T is the integrator constant (i.e.

integrator time constant);

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C - integration time. With and _{% b | H} = O

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Analysis of the expression shows that the resolution of this method of converting the input voltage and, in the time interval b, increases in the approximation and, to the reference voltage, and ₂ . '

Based on this, that the amplifier 1 with the elements 2,3,5-8, 10-13,

16 and 17 can be considered as one block, and block 4 as another, the specific hardware costs for one realizable ’function will be approximately 0.22 blocks, i.e. significantly lower than for traditional analog circuits.

Claims (1)

Claim Analog storage device containing an amplifier, a first accumulator element on a capacitor, first and second restrictive elements on diodes, first and second passive elements on resistors, first to sixth key elements whose control inputs are respectively control inputs of the device, the first capacitor plate of the first storage element is connected to the output of the amplifier and is the information output of the device, the second capacitor plate is connected to the inverting input spruce and the first output of the first passive resistor element, the second output of which is connected to the information output of the third key element, the cathode The first diode and the anode of the second limiting element diode are connected to the information input of the first key element, characterized in that, in order to improve the accuracy and enhance the functionality by implementing various processing and analogue data conversion operations, a memory block is inserted in it, the second a storage element on a capacitor, the first lining of which is connected to the bus. zero potential, and the second to the non-inverting input of the amplifier, informational 20 outputs of the first, fourth, fifth and sixth key elements, information input and output of the second key element are connected respectively to the first and second plates 25 of the capacitor of the first storage element, the information input of the first key element is the first information input of the device, the anode of the first diode and the cathode The 20 diodes of the second limiting elements are connected respectively to the information inputs of the fourth and fifth key elements, the information input of the third key element is connected to the output of the memory block whose input is the second information input of the device, the first and second terminals of the resistor of the second passive element ^ 0 are respectively to the information input of the sixth key element and to the tire of zero potential.