WO2002045256A1 - Self-compensating buffer amplifier - Google Patents

Self-compensating buffer amplifier Download PDF

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Publication number
WO2002045256A1
WO2002045256A1 PCT/GB2001/005271 GB0105271W WO0245256A1 WO 2002045256 A1 WO2002045256 A1 WO 2002045256A1 GB 0105271 W GB0105271 W GB 0105271W WO 0245256 A1 WO0245256 A1 WO 0245256A1
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WIPO (PCT)
Prior art keywords
voltage
output
storage capacitor
buffer amplifier
threshold voltage
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Application number
PCT/GB2001/005271
Other languages
French (fr)
Inventor
Michael John Lee
Alison Burdett
Yung Chin Chen
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Imperial College Of Science
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Publication date
Application filed by Imperial College Of Science filed Critical Imperial College Of Science
Priority to AU2002220845A priority Critical patent/AU2002220845A1/en
Publication of WO2002045256A1 publication Critical patent/WO2002045256A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • This invention relates to a clocked unity gain buffer amplifier, particularly useful in driving devices such as flat panel displays.
  • it has the advantage that its fabrication can be integrated easily with that of the display in a thin film process on a glass substrate, without greatly increasing the number of necessary process steps or the complexity of the process.
  • the present invention seeks to provide a construction for a unity gain buffer amplifier which can compensate for differences in threshold voltage, by making the output voltage of the amplifier independent of the threshold voltage.
  • a clocked buffer amplifier circuit including a storage capacitor which is arranged to be pre-charged to a voltage which matches the threshold voltage of an output transistor, so that the offset effect of the threshold voltage can be compensated, at the output of the amplifier.
  • the amplifier comprises (a) an output transistor whose source electrode comprises the output of the amplifier,
  • the amplifier comprises:
  • the second transistor of the output pair is arranged to act as a discharge circuit for the voltage at the output of the amplifier, the arrangement being such that the discharge transistor is switched on before charging of the storage capacitor begins. This ensures that the difference between the reference voltage and the output voltage is sufficient to charge the storage capacitor.
  • the output stage, and all of the switching devices are MOSFETS of the same type.
  • Figure 1a is a circuit diagram of a source-follower buffer amplifier
  • Figure 1 b is a clock pulse scheme for the amplifier of Figure 1a;
  • Figure 2a is an equivalent circuit illustrating operation during clock ⁇ r ;
  • Figure 2b is an equivalent circuit showing operation during clock ⁇ 1 ;
  • Figure 2c is an equivalent circuit showing operation during clock ⁇ 2;
  • Figure 4 is a circuit for generating selectable reference voltages.
  • the buffer amplifier consists of seven same type devices, a reference voltage V r , and a threshold-holding capacitor C t .
  • C L represents the load capacitance.
  • ⁇ r is a reset pulse which turns switch T6 on first and thus discharges the data on 0. via discharge transistor T5 at the beginning of the column select period, see Figure 2(a).
  • the reset pulse is required because capacitor C t will only be charged up as required during the precharge phase ⁇ 1 if V r is greater than the previous value of V out .
  • V out is always discharged via T5/T6 by applying ⁇ r before the charging of C t begins during ⁇ 1.
  • V ou t value is close to V ss , i.e. the initial value of V out is approximately equal to V ss .
  • T5 is held off by ⁇ 3 via T7, thus no discharge of C L (or C t ) can occur once T4 stops conducting as illustrated in Figure 2(b).
  • T1/T2/T3/T4/T5/T6/T7 8/8:8/8:8/8:160/8:8/8:8/8:8/8:8/8:8/8, and the threshold voltage of devices is 3V. Buffer output values showing that the output voltage deviation is within ⁇ 20mV in each case, i.e. 8 bit resolution is achievable.
  • the basic functionality of the unity gain buffer amplifier, for Vip n 6V, is also shown in Figure 3.
  • V r is necessary since during ⁇ 1 , charge transfer from V r to C t occurs. If C t was connected to V in during ⁇ 1 , there would be charge transfer from the sample and hold capacitor onto C t , thus Vj n would reduce.
  • the accuracy of the circuit operation can thus be increased by using a plurality of reference voltages V r1 , V r2 ... V rn , as shown in Figure 4.
  • V r1 , V r2 ... V rn the reference voltage which is closest to the value of V fn is selected.
  • the reference control signals which select the required reference value may be generated either off or on the glass substrate.
  • One possible fully-NMOS implementation is shown in the drawing, in which four separate reference values V r1 -V r4 are available.
  • control signals b1-b4 determine which of the reference voltages is selected by switching devices M1-M4 on or off.
  • the control signals may be generated off-glass and then delivered to each column by four off-glass wire connections.
  • the control signals are held in a four-bit latch, the values being written into the column latch at the same time as the input signal V in is being sampled onto that column's sample-and-hold capacitor.
  • the required value of V r may be fed onto the glass substrate as an analogue value on a single line.
  • ADC analog-to-digital converter

Abstract

A clocked buffer amplifier circuit which is adapted to reduce the error between the input and the output by compensating for possible variations in the threshold voltage of an output transistor, the circuit including a storage capacitor which is arranged to be pre-charged to a voltage which matches the threshold voltage of the output transistor, so that the offset effect of the threshold voltage can be compensated, at the output of the amplifier.

Description

Self-Compensating Buffer Amplifier
This invention relates to a clocked unity gain buffer amplifier, particularly useful in driving devices such as flat panel displays. In particular, it has the advantage that its fabrication can be integrated easily with that of the display in a thin film process on a glass substrate, without greatly increasing the number of necessary process steps or the complexity of the process.
One of the common problems of producing effective buffer amplifiers in applications of this kind, is that thin film devices do not have very consistent operating characteristics, so that, for example, the threshold voltage varies widely between different transistors on the same substrate. The present invention seeks to provide a construction for a unity gain buffer amplifier which can compensate for differences in threshold voltage, by making the output voltage of the amplifier independent of the threshold voltage.
According to a first feature of the invention, therefore, there is provided a clocked buffer amplifier circuit including a storage capacitor which is arranged to be pre-charged to a voltage which matches the threshold voltage of an output transistor, so that the offset effect of the threshold voltage can be compensated, at the output of the amplifier.
Preferably, therefore, the amplifier comprises (a) an output transistor whose source electrode comprises the output of the amplifier,
(b) first switching means for connecting a storage capacitor across the gate and source of the output transistor whilst a reference voltage is applied to the gate, whereby the storage capacitor can be charged to a voltage which matches the threshold voltage of the output transistor; and
(c) second switching means for disconnecting the storage capacitor from the output, and instead, connecting it so that its voltage is summed with an input voltage signal, so that any drop in the output voltage, caused by the threshold voltage of the output transistor, is compensated by the stored voltage on the storage capacitor.
In a preferred arrangement, the amplifier comprises:
(a) an output stage comprising a pair of MOSFET transistors arranged in a source follower connection,
(b) a storage capacitor having one side connected to the gate of the source follower output transistor;
(c) a first switching device connected to the said one side of the storage capacitor, and adapted to connect it to a reference voltage; (d) a second switching device connected to the other side of the capacitor, and adapted to connect it to an input voltage source;
(e) a third switching device adapted to connect the other side of the capacitor to the output of the source follower; and
(f) a suitable supply of clock pulses for the switching devices, whereby the first and third switching devices are switched on to pre-charge the capacitor, to the threshold voltage of the source follower transistor, by the application of the reference voltage, whilst the second switching device is held off; and the second switching device is then switched on, whilst the first and third switching devices are held off, so as to apply the input voltage and the storage capacitor voltage to the input of the source follower output stage, so that the output voltage then accurately reflects the input voltage as a result of the compensation of the threshold voltage by the capacitor voltage.
Preferably, the second transistor of the output pair is arranged to act as a discharge circuit for the voltage at the output of the amplifier, the arrangement being such that the discharge transistor is switched on before charging of the storage capacitor begins. This ensures that the difference between the reference voltage and the output voltage is sufficient to charge the storage capacitor. Preferably the output stage, and all of the switching devices are MOSFETS of the same type.
One embodiment of the invention will now be described with reference to the accompanying drawings, in which: Figure 1a is a circuit diagram of a source-follower buffer amplifier;
Figure 1 b is a clock pulse scheme for the amplifier of Figure 1a;
Figure 2a is an equivalent circuit illustrating operation during clock φr;
Figure 2b is an equivalent circuit showing operation during clock φ1 ;
Figure 2c is an equivalent circuit showing operation during clock φ2; Figure 3 is a chart showing input and output voltages for the Vin=6V; and
Figure 4 is a circuit for generating selectable reference voltages.
As illustrated in Figure 1 , the buffer amplifier consists of seven same type devices, a reference voltage Vr, and a threshold-holding capacitor Ct. CL represents the load capacitance. The principle of operation of the buffer in a typical application, as a display column driver, is shown in Figure 2 and outlined as follows: φr is a reset pulse which turns switch T6 on first and thus discharges the data on 0. via discharge transistor T5 at the beginning of the column select period, see Figure 2(a). The reset pulse is required because capacitor Ct will only be charged up as required during the precharge phase φ1 if Vr is greater than the previous value of Vout. Thus Vout is always discharged via T5/T6 by applying φr before the charging of Ct begins during φ1. During φr, Vout value is close to Vss, i.e. the initial value of Vout is approximately equal to Vss.
During the precharge phase φ1 , switches T1 , T2 and T7 are turned on and the circuit is configured as in Figure 2(b). A reference voltage Vr (greater than the initial value of Vouf «VSS) is applied to charge up C via T1 and T2, and CL via T4, thus increasing the voltage at the source of T4 and thereby reducing Vgs of T4. T4 will turn off when Vgs4=Vtr,4, where Vgs4 and Vth are the gate-source and threshold voltages of T4, respectively. So that at this time Vout =Vg4-Vtn4, where Vg4 is the gate voltage of T4. At the end of φ1 , assuming that
Figure imgf000006_0001
(Vdsiφi and Vds2φ1 are the Vds values of T1 and T2 measured at the end of φ1 ),
Vx=Vr=Vg4
Figure imgf000006_0002
thus Vx-Vy=Vr-(Vr-Vth4)=Vth4 Therefore the voltage stored on Ct is approximately equal to the threshold voltage of T4. T5 is held off by φ3 via T7, thus no discharge of CL (or Ct) can occur once T4 stops conducting as illustrated in Figure 2(b).
The reference voltage Vr is necessary since during φ1 , there would be charge transfer from the sample and hold storage capacitor onto C , thus Vin would reduce. During φ2, switch T3 is now on and the circuit is configured as in Figure 3(c).
The charge Qt=Vth .Ct remains stored on Ct, i.e. the voltage difference between Vx and Vy across C is held constant. Since Vy is now connected to Vin, Vg is pulled up to in+Vth4 causing T4 to conduct and CL to charge up further thus increasing the voltage of the source of T4 and thereby reducing Vgs4. As in the φ1 cycle T4 will turn off when gs =Vth4. After this time φ2 is turned off, and
Figure imgf000006_0003
Since the voltage difference across Ct is held constant, the output voltage therefore follows the input with no error, i.e. V0Ut=Vin. Therefore the threshold voltage of T4 does not need to be accurately known since it is stored on Ct during φ1 and φ2, T7 is on via φ3(=φ1+φ2) holding T5 off and preventing discharge of the output voltage.
The accuracy of the buffer transfer function for a given load capacitance will depend on the device characteristics and dimensions and value of the storage capacitor. As an example of the invention, Table 1 shows the HSPICE simulation results for the following selected values, Vdd/Vss=+12V/-12V, Vr=0V, VΦ=±16V,
Ct=3pF, clock scheme φr/φ1/φ2=2μs/18μs/20μs, the W/L ratio of devices
T1/T2/T3/T4/T5/T6/T7=8/8:8/8:8/8:160/8:8/8:8/8:8/8, and the threshold voltage of devices is 3V. Buffer output values showing that the output voltage deviation is within ±20mV in each case, i.e. 8 bit resolution is achievable. The basic functionality of the unity gain buffer amplifier, for Vipn=6V, is also shown in Figure 3.
As mentioned above, the reference voltage Vr is necessary since during φ1 , charge transfer from Vr to Ct occurs. If Ct was connected to Vin during φ1 , there would be charge transfer from the sample and hold capacitor onto Ct, thus Vjn would reduce.
In practice the threshold voltage Vtrι of a TFT is found to vary slightly with the value of drain-source voltage Vds. Therefore to ensure that Vtrι(φ1 ) = Vtr,(φ1 ) = Vtrι(φ2), the transistor should ideally operate with the same value of Vds during φ1 and φ2. In other words, the reference voltage Vr applied during the precharge phase φ1 should be as close as possible to the value of the input voltage Vin applied during the following output phase φ2.
The accuracy of the circuit operation can thus be increased by using a plurality of reference voltages Vr1, Vr2 ... Vrn, as shown in Figure 4. During φ1 , the reference voltage which is closest to the value of Vfn is selected. The reference control signals which select the required reference value may be generated either off or on the glass substrate. One possible fully-NMOS implementation is shown in the drawing, in which four separate reference values Vr1-Vr4 are available.
These reference voltages are distributed either linearly or nonlineariy over the dynamic range of the input signal, such that: Viπ (min) <' Vr1 < Vr2 < Vr3 < Vr4 < Vin (max)
The control signals b1-b4 determine which of the reference voltages is selected by switching devices M1-M4 on or off.
The control signals may be generated off-glass and then delivered to each column by four off-glass wire connections. In this case, the control signals are held in a four-bit latch, the values being written into the column latch at the same time as the input signal Vin is being sampled onto that column's sample-and-hold capacitor. Alternatively, the required value of Vr may be fed onto the glass substrate as an analogue value on a single line. In this case, a four bit analog-to-digital converter (ADC) at each column will locally generate the required b1-b4 digital values.

Claims

1. A clocked buffer amplifier circuit which is adapted to reduce the error between the input and the output by compensating for possible variations in the threshold voltage of an output transistor, the circuit including a storage capacitor which is arranged to be pre-charged to a voltage which matches the threshold voltage of the output transistor, so that the offset effect of the threshold voltage can be compensated, at the output of the amplifier.
2. A clocked buffer amplifier according to claim 1 in which the circuit comprises: (a) an output transistor whose source electrode comprises the output of the amplifier,
(b) first switching means for connecting a storage capacitor across the gate and source of the output transistor whilst a reference voltage is applied to the gate, whereby the storage capacitor can be charged to a voltage which matches the threshold voltage of the output transistor; and
(c) second switching means for disconnecting the storage capacitor from the output, and instead, connecting it so that its voltage is summed with an input voltage signal, so that any drop in the output voltage, caused by the threshold voltage of the output transistor, is compensated by the stored voltage on the storage capacitor.
3. A clocked buffer amplifier circuit according to claim 1 or claim 2 and comprising:
(a) an output stage comprising a pair of MOSFET transistors arranged in a source follower connection, (b) a storage capacitor having one side connected to the gate of the source follower output transistor; (c) a first switching device connected to the said one side of the storage capacitor, and adapted to connect it to a reference voltage;
(d) a second switching device connected to the other side of the capacitor, and adapted to connect it to an input voltage source; - (e) a third switching device adapted to connect the other side of the capacitor to the output of the source follower; and
(f) a suitable supply of clock pulses for the switching devices, whereby the first and third switching devices are switched on to pre-charge the capacitor, to the threshold voltage of the source follower transistor, by the application of the reference voltage, whilst the second switching device is held off; and the second switching device is then switched on, whilst the first and third switching devices are held off, so as to apply the input voltage and the storage capacitor voltage to the input of the source follower output stage, so that the output voltage then accurately reflects the input voltage as a result of the compensation of the threshold voltage by the capacitor voltage.
4. A clocked buffer amplifier according to claim 3, further comprising means for generating a range of selectable reference voltages, and means for selecting the reference voltage so as to match the input voltage source as closely as possible.
5. A clocked buffer amplifier circuit according to claim 3 or claim 4, further comprising: switching means arranged to discharge the voltage at the output of the amplifier, before charging of the storage capacitor begins, so as to ensure that the difference between the reference voltage and the output voltage is sufficient to charge the storage capacitor.
6. A clocked buffer amplifier circuit according to any one of claims 2 to 5 in which the output stage and all of the switching devices are MOSFETS of the same type.
7. An LSI circuit including a plurality of buffer amplifier circuits according to any preceding claim.
8. A display device including an array of thin film transistors driven by buffer amplifiers according to any of claims 1 to 6.
PCT/GB2001/005271 2000-11-30 2001-11-28 Self-compensating buffer amplifier WO2002045256A1 (en)

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GB0029245.8 2000-11-30

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1303756C (en) * 2003-03-25 2007-03-07 三菱电机株式会社 Offset compensation circuit and drive circuit and liquid crystal display device using it
US7460634B2 (en) 2004-07-31 2008-12-02 Koninklijke Philips Electronics N.V. Shift register circuit
CN110738974A (en) * 2019-10-28 2020-01-31 京东方科技集团股份有限公司 Liquid crystal pixel circuit, driving method thereof, display panel and display device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103618522A (en) * 2013-11-26 2014-03-05 苏州贝克微电子有限公司 Self-adaptation threshold value circuit of comparator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2157108A (en) * 1984-04-02 1985-10-16 Gen Electric Eliminating input offset
US4942367A (en) * 1989-09-29 1990-07-17 General Electric Company Auto-zeroing switched-capacitance buffer amplifiers with minus-unity voltage gain

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2157108A (en) * 1984-04-02 1985-10-16 Gen Electric Eliminating input offset
US4942367A (en) * 1989-09-29 1990-07-17 General Electric Company Auto-zeroing switched-capacitance buffer amplifiers with minus-unity voltage gain

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1303756C (en) * 2003-03-25 2007-03-07 三菱电机株式会社 Offset compensation circuit and drive circuit and liquid crystal display device using it
US7460634B2 (en) 2004-07-31 2008-12-02 Koninklijke Philips Electronics N.V. Shift register circuit
CN110738974A (en) * 2019-10-28 2020-01-31 京东方科技集团股份有限公司 Liquid crystal pixel circuit, driving method thereof, display panel and display device

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GB0029245D0 (en) 2001-01-17
AU2002220845A1 (en) 2002-06-11

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