JPH1049110A - Sample-hold circuit, data driver using it and flat panel display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dispersion in an input/output voltage characteristic even when the dispersion exists in a threshold value of an FET. SOLUTION: A sample-hold circuit that a hold capacitor CH1 is connected between a gate of a source follower circuit 30 and a grounded line, and an analog switch 31 is connected between the gate and the input end of the sample- hold circuit is provided with a corrective capacitor CC1 whose one end is connected to the gate, an analog switch 33 connected between the other end of the corrective capacitor CC1 and the source and the analog switch 34 connected between the other end of the corrective capacitor CC1 and a reference potential line Vref. A voltage sampled and held to the hold capacitor CH1 is subtracted and corrected according to a threshold value Vth of an nMOS transistor detected by the corrective capacitor CC1, and an output voltage before correction VSA-Vth is lowered further by ΔV by correction. When the Vth is small, the ΔV becomes large, and when the Vth is large, the ΔV becomes small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, a data driver using the same, and a flat panel display device.

[0002]

2. Description of the Related Art FIG. 7 shows an entire configuration of a conventional liquid crystal display device. In FIG. 7, for simplicity, the liquid crystal display panel 10
Shows a pixel configuration of 4 rows and 5 columns. In the liquid crystal display panel 10, a pair of glass substrates are arranged so as to face each other, and display electrodes of liquid crystal pixels 11 are arranged in a matrix on one of the glass substrates.
The thin film transistor 12 is formed for each of the first to fourth rows of the thin film transistor 12,
To 144 are formed, and the first to fifth of the thin film transistor 12 are formed.
Data electrodes 131 to 135 are formed on the columns at right angles to the scan electrodes 141 to 144 via an insulating film. On the other glass substrate, a transparent solid electrode Vcom common to each liquid crystal pixel 11 (a counter electrode Vcom for the display electrode)
Are formed. To the electrode Vcom, a signal for alternately inverting the video signal VSA to a positive potential and a negative potential every one horizontal period to prevent liquid crystal deterioration is supplied.

[0003] The data electrodes 131 to 135 are connected to the output terminal of the data driver 20, and the scan electrodes 141 to 144 are connected to the output terminal of the scan driver 21. Based on the supplied dot clock CLK, the video signal VS not including the synchronization signal, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC, the control circuit 22 has the same frequency as the start pulse ST and the dot clock CLK whose cycle is one horizontal period. The clock CK1, the amplified video signal VSA, and the latch signal LT are generated and supplied to the data driver 20, and a signal for scanning the scan electrodes in one horizontal period is supplied to the scan driver 21.

The data driver 20 includes a dot-sequential scanning shift register 23, a sample hold circuit 24, and a sample hold circuit 25. Shift register 23 corresponding to data electrode 131, sample hold circuit 2
4 and component 2 for one column of sample-and-hold circuit 25
FIG. 8 shows a configuration example of the sample hold circuits 241 and 251.

The analog switch 31 is connected between the signal input terminal of the sample hold circuit 241 and the input terminal of the buffer circuit 30. Analog switch 31
Is a transfer gate in which a pMOS transistor and an nMOS transistor are connected in parallel, and is turned on / off by a selection signal S1 and a signal obtained by inverting the selection signal S1 by an inverter 32. The hold capacitor CH1 is connected between the input terminal of the buffer circuit 30 and the ground line. The sample hold circuit 251 is
And the buffer circuit 40 of the sample and hold circuit 251, the analog switch 41, and the inverter 42.
The hold capacitor CH2 corresponds to the buffer circuit 30, the analog switch 31, the inverter 32, and the hold capacitor CH1 of the sample / hold circuit 241, respectively.

First, the analog switch 31 is turned off when the selection signal S1 is at a low level. Start pulse ST
Transitions to a high level, which is held in the D flip-flop 231 at the rise of the clock CK1, the Q output selection signal S1 goes high, the analog switch 31 is turned on, and the voltage of the video signal VSA is held. It is sampled by the capacitor CH1. The start pulse ST goes low, the selection signal S1 is held low at the next rise of the clock CK1, the analog switch 31 is turned off, and the hold capacitor CH
The voltage sampled at 1 is held. From the buffer circuit 30, a pixel signal VD1 having a voltage corresponding to the voltage of the hold capacitor CH1 is taken out.

In FIG. 7, the video signal V for one row in one horizontal period is obtained by dot sequential scanning by the shift register 23.
SA is sampled and held by the sample and hold circuit 24, and then the output of the sample and hold circuit 24 is held by the sample and hold circuit 25 by the latch signal LT.
In this state, the video signal VSA for one row is sampled and held by the sample and hold circuit 24 in one horizontal period by dot sequential scanning by the shift register 23. Hereinafter, the same processing is repeated.

[0008] The data driver 20 is a liquid crystal display panel 1
It is preferable in terms of manufacturing cost that the thin film transistor 12 is formed around the liquid crystal display panel 10 in the same step as the step of forming the thin film transistor 12 of zero. Buffer circuit 30
And 40 have a high input impedance and a low output impedance, and are generally constituted by a voltage follower with an amplification factor of 1 connecting an inverting input terminal and an output terminal of an operational amplifier circuit.

However, thin film transistors formed on a glass substrate have relatively large variations in characteristics, and even if they are adjacent to each other, the threshold voltage (gate-source voltage when a drain current starts to flow) is different. In addition, the input / output voltage characteristics of the voltage follower greatly vary, and even if the input voltage is the same, the output voltage differs for each data electrode, resulting in poor display quality.

Therefore, when the thin film transistor 20 is formed, a source follower circuit as shown in FIG. The input and output of the buffer circuit 30 are the gate and source of the nMOS transistor N1, respectively, and a current always flows through the resistor R1.
The buffer circuit 40 is similar to the buffer circuit 30.

[0011]

Although the variation in the input / output voltage characteristics of the source follower circuit is smaller than that of the voltage follower, the variation in the threshold value of the nMOS transistor N1 results in the variation in the input / output characteristics of the source follower circuit. Therefore, it is inevitable that the display quality is reduced.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a sample-and-hold circuit capable of further reducing variations in input / output voltage characteristics even if the thresholds of FETs vary, and to use the same. To provide a data driver and a flat panel display device.

[0013]

In the sample and hold circuit according to the present invention, the output stage has a source follower circuit having an input terminal and an output terminal of a gate and a source of the FET, respectively. A sample-and-hold circuit in which a hold capacitor is connected between the gate and one reference potential and a first analog switch is connected between the gate and an input terminal of the sample-and-hold circuit; A capacitor, a second analog switch connected between the other end of the correction capacitor and the source, and a third analog switch connected between the other end of the correction capacitor and a second reference potential. Have.

In the above configuration, for example, it is assumed that first and second analog switches are turned off and the third analog switch is turned on first. When the first and second analog switches are turned on from this state, the voltage VSA of the input signal is sampled by the hold capacitor, and the voltage of the correction capacitor becomes equal to the threshold value Vth of the FET.

Next, when the first and second analog switches are turned off and the third analog switch is turned on, the electric charge ΔQ moves from the hold capacitor to the correction capacitor, the voltages of both capacitors become equal, and the sample hold The output voltage VD1 of the circuit decreases by ΔV. This allows
VD1 = VSA− (Vth + ΔV) Charge transfer amount Δ
Since Q is larger as the threshold value Vth is smaller, the smaller the threshold value Vth is, the larger the voltage drop of the hold capacitor is, and the larger the decrease amount ΔV of the output voltage VD1 is.

Therefore, by appropriately selecting the capacitance ratio between the hold capacitor and the correction capacitor and the reference potential, the voltage (Vth + ΔV) can be made substantially constant regardless of the variation in the threshold value Vth of the FET. Output voltage V with respect to input voltage VSA of sample and hold circuit
There is an effect that variation in the characteristics of D1 can be reduced.

According to a first aspect of the present invention, there is provided a control circuit,
The control circuit includes the first analog switch and the second analog switch.
Turning on the analog switch and turning off the third analog switch, then the first analog switch and the second
The analog switch is turned off and the third analog switch is turned on.

According to a second aspect of the present invention, there is provided a control circuit,
The control circuit includes: (1) turning on the first analog switch and the second analog switch, turning off the third analog switch, (2) then turning off the first analog switch, (3) then turning on the first analog switch. The second analog switch is turned off and the third analog switch is turned on, and the time from the start of operation (2) to the start of operation (3) is used as a correction parameter.

According to the second aspect, the output voltage of the sample-and-hold circuit is not corrected from the start of the operation in (2) to the start of the operation in (3), and the output voltage of the sample-and-hold circuit after the start of the operation in (3). Is effective when the average value of one cycle of the output is significant as in a sample and hold circuit connected to the data electrode of the liquid crystal display device. This has the effect of further reducing the variation in the input / output voltage characteristics of the circuit.

In the data driver according to the third aspect of the present invention,
The liquid crystal display device includes one of the sample and hold circuits provided corresponding to each data electrode and having an output terminal connected to the data electrode, and an FET of the sample and hold circuit.
Are formed of thin film transistors. According to the third aspect, a liquid crystal display panel using a thin film transistor as a pixel switch as a sample and hold circuit and a sample and hold circuit with reduced variation in input / output voltage characteristics can be manufactured in the same process. There is an effect that the manufacturing cost of the display device can be reduced.

[0021] A flat panel display device according to a fourth aspect of the present invention includes any of the sample and hold circuits described above, and a display flat panel in which an output terminal of the sample and hold circuit is connected to a data electrode.

According to the fourth aspect, since the variation in the input / output voltage characteristics of the sample-and-hold circuit is reduced, the display quality of the flat panel display is improved.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a sample and hold circuit according to an embodiment of the present invention. Buffer circuit 30
Is a source follower circuit, and an nMOS transistor N
One gate and one source are an input terminal and an output terminal of the buffer circuit 30, respectively. nMOS transistor N
1 is connected to the ground line via the resistor R1, and the drain of the nMOS transistor N1 is connected to the power supply line VCC. Between the gate of the nMOS transistor N1 and the input terminal of the sample-and-hold circuit, an analog switch 3 that is turned on / off by a selection signal S1
1 is connected. A hold capacitor CH1 is connected between the gate of the nMOS transistor N1 and the ground line.
Is connected. The above configuration is the same as the conventional one.

The configuration of this embodiment is characterized in that one end of the correction capacitor CC1 is connected to the gate of the nMOS transistor N1, and the other end of the correction capacitor CC1 is connected to the nMOS transistor N1 via the analog switch 33.
And the other end is connected to the reference potential line Vref via the analog switch 34.
The analog switches 33 and 34 respectively control the control signal S
On / off control is performed in 2 and S3.

Next, the operation of the present embodiment configured as described above will be described with reference to FIG. FIG. 2 (A) to (C)
Shows the on / off waveforms of the analog switches 31, 33 and 34, respectively, and FIGS. 2D and 2E show the input / output voltage waveforms of the sample and hold circuit. VSA and VD1
Is an input signal and an output signal of the sample hold circuit, respectively. 2D differs from FIG. 2E in the threshold value Vth of the nMOS transistor N1, and FIG.
The case where the threshold value Vth is larger than (E) is shown.

First, it is assumed that the analog switches 31 and 33 are off and the analog switch 34 is on.
When the analog switches 31 and 33 are turned on from this state, the voltage of the input signal VSA changes to the value of the hold capacitor CH.
1 and the voltage of the correction capacitor CC1 becomes equal to the threshold value Vth of the nMOS transistor N1.

Next, when the analog switches 31 and 33 are turned off and the analog switch 34 is turned on, the electric charge ΔQ is transferred from the hold capacitor CH1 to the correction capacitor CC1 because the voltage of the correction capacitor CC1 is lower than the voltage of the hold capacitor CH1. Moving, the two voltages become equal, and the voltage VD1 decreases by ΔV. Thereby, VD
1 = VSA− (Vth + ΔV) Charge transfer amount ΔQ
Is larger as the threshold value Vth is smaller,
The smaller the th is, the larger the voltage drop of the hold capacitor CH1 is, and the larger the decrease ΔV of the voltage VD1 is.

Therefore, the capacitance ratio between the hold capacitor CH1 and the correction capacitor CC1 and the reference potential line Vref
Is properly selected, the nMOS transistor N
1 (Vth + Δ
V) can be made substantially constant, and variations in the characteristics of the output voltage VD1 with respect to the input voltage VSA of the sample and hold circuit can be reduced.

[0029]

【Example】

FIG. 3 shows a sample and hold circuit according to a first embodiment of the present invention. In this circuit, the analog switch 31 in FIG. 1 is configured by a transfer gate in which an nMOS transistor and a pMOS transistor are connected in parallel, and the analog switches 33 and 34 in FIG. 1 are each configured by an nMOS transistor, and a reference potential line Vref Is the ground line. Also, the gate of the nMOS transistor and the gate of the pMOS transistor of the analog switch 31, respectively,
A selection signal S1 and a signal * S1 obtained by inverting the selection signal S1 by an inverter 32 are supplied to the nMOS transistor 3
The control signal S3 is supplied to the gate of the nMOS transistor 4 and the signal S2 obtained by inverting the control signal S3 by the inverter 35 is supplied to the gate of the nMOS transistor 33.

The other points are the same as in FIG. FIG. 4 shows a sample and hold circuit according to a second embodiment of the present invention. In this circuit, the hold capacitor CH1 in FIG. 3 is omitted, and the gate capacitance of the nMOS transistor N1 is replaced with the hold capacitor CH1.
Used as

The other points are the same as in FIG. Third Embodiment FIG. 5 shows a two-stage sample-hold circuit according to a third embodiment of the present invention. This circuit is used for the data driver of the liquid crystal display device of FIG. 7, and the sample and hold circuits 241A and 251A correspond to the sample and hold circuits 241 and 251 of FIG. 8, respectively.

The sample and hold circuit 241A has a configuration in which a capacitor C for increasing the driving capability is connected to the output terminal of the sample and hold circuit of FIG. The sample and hold circuit 251A has the same configuration as the sample and hold circuit 241A except for the capacitor C. The sample and hold circuit 251A has an nMOS transistor N2, a resistor R2, a hold capacitor CH2, an analog switch 41, an inverter 42, and a correction capacitor. C
C2, nMOS transistors 43 and 44 as an analog switch, an inverter 45, a latch signal LT, a control signal S4 and a signal VD2 are respectively an nMOS transistor N1, a resistor R1, a hold capacitor CH1, an analog switch 31, an inverter 32 of the sample and hold circuit 241A, Correction capacitor CC1, nMOS transistors 33 and 34 as analog switches, inverter 3
5, corresponding to the control signals S1, S3 and the signal VD1.

The output terminal of the sample hold circuit 251A is connected to one electrode of the liquid crystal pixel 11 via a data electrode. Also, the signals LT, VSA, S3 and S4
Is supplied from a control circuit 22A corresponding to the control circuit 22 in FIG. The latch signal and the selection signal S1 are the same as those in FIG. Next, the operation of the two-stage sample-hold circuit configured as described above will be described with reference to FIG.

First, when the selection signal S1 is at a low level, the analog switch 31 is off, and when the control signal S3 is at a high level, nMO
S transistor 33 is off, nMOS transistor 34
Is on, the latch signal LT is low, the analog switch 41 is off, the control signal S4 is low, the nMOS transistor 44 is off, and the nMOS transistor 43 is on. In this state, the nMOS transistor 44
Is off, the output signal VD2 of the sample-and-hold circuit 251A is not corrected by the correction capacitor CC2 and is the same as the conventional one.

(T1) The selection signal S1 changes to a high level to turn on the analog switch 31, and at the same time, the control signal S3 changes to a low level to turn off the nMOS transistor 34 and turn on the nMOS transistor 33. .
As a result, the voltage of the input signal VSA is sampled by the hold capacitor CH1, and the voltage of the correction capacitor CC1 becomes equal to the threshold value Vth of the nMOS transistor N1.

(T2) The selection signal S1 transitions to a low level to turn off the analog switch 31, and at the same time, the control signal S3 transitions to a high level to turn on the nMOS transistor 34 and turn off the nMOS transistor 33. .
As a result, the charge moves from the hold capacitor CH1 to the correction capacitor CC1, and as described above, the voltage of the signal VD1 is corrected according to the threshold value Vth of the nMOS transistor N1, and the output of the sample and hold circuit 241A with respect to the input signal VSA is output. Variations in the characteristics of the signal VD1 are reduced.

(T3) The control signal S4 transitions to the high level, turning on the nMOS transistor 44 and turning off the nMOS transistor 43. As a result, charges move from the hold capacitor CH2 to the correction capacitor CC2, and as described above, the threshold voltage Vth of the nMOS transistor N2
, The voltage of the output signal VD2 is corrected by ΔV, and the variation in the characteristics of the output voltage VD2 with respect to the input voltage VD1 of the sample hold circuit 251A is reduced.

The output voltage VD in a period T from the rise of the latch signal LT to the rise of the next latch signal LT.
2 corresponds to the luminance of the liquid crystal pixel, the correction start time t3 of the sample and hold circuit 251A
Is added to one of the parameters of the variation reduction,
By appropriately setting the correction start time t3, the variation in the input / output voltage characteristics of the sample and hold circuit 251A can be further reduced.

(T4) The latch signal LT changes to a high level to turn on the analog switch 41, and at the same time, the control signal S4 changes to a low level to turn off the nMOS transistor 44 and turn on the nMOS transistor 43. . As a result, the corrected signal VD1 is sampled by the hold capacitor CH2, and the corrected capacitor CC is
2 becomes equal to the threshold value Vth of the nMOS transistor N2.

(T5) The latch signal LT transits to a low level, the analog switch 41 is turned off, and the voltage of the hold capacitor CH2 is held. The output signal VD2 is
The voltage becomes a voltage corresponding to the hold capacitor CH2 before correction by the correction capacitor CC2. The above processing is repeatedly performed.

The present invention also includes various modifications. For example, the present invention is suitable for a sample-and-hold circuit using a thin film transistor having a relatively large variation in threshold value. However, even for FETs other than the thin film transistor, generally the threshold value varies and high accuracy is required. It is also effective when applied to a sample and hold circuit.

The source follower circuit 30 only needs to have an input impedance higher than the output impedance and a source potential lower than the gate potential by the threshold value Vth, and use a constant current source instead of the resistor R1. You may. The hold capacitor only has to have the voltage holding function substantially, and the gate capacitance as in the case of FIG. 4 is also included in the hold capacitor.

Even when the present invention is applied to a data driver of a liquid crystal display device, a data driver having another configuration, for example, a sample-and-hold circuit is connected in parallel, and one of the sample-and-hold circuits converts the input signal VSA. The present invention can be applied to a data driver having a configuration in which the output of the other sample and hold circuit is supplied to the data electrode during sampling and the roles of both sample and hold circuits are alternately switched.

Further, in the various flat panel display devices including the liquid crystal display device, if the sample and hold circuit of the present invention is connected to the data electrodes of the panel, the variation of the output voltage characteristic with respect to the input voltage of the sample and hold circuit can be reduced. Therefore, display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a sample and hold circuit according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the circuit of FIG.

FIG. 3 is a diagram showing a sample and hold circuit according to a first embodiment of the present invention.

FIG. 4 is a diagram illustrating a sample and hold circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a two-stage sample-hold circuit used in a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the circuit of FIG.

FIG. 7 is an overall configuration diagram of a conventional liquid crystal display device.

FIG. 8 is a diagram showing a two-stage sample-and-hold circuit used in the data driver of FIG. 7;

9 is a diagram illustrating a source follower circuit used as a buffer circuit in the sample and hold circuit of FIG. 8;

[Explanation of symbols]

231 D flip-flop 241, 241A, 251, 251A Sample hold circuit 30 Buffer circuit 31, 33, 34, 41, 43, 44 Analog switch 32, 35, 42, 45 Inverter CH1, CH2 Hold capacitor CC1, CC2 Correction capacitor N1, N2 nMOS transistor R1, R2 resistance

Continuation of the front page (72) Inventor Kenichi Nakabayashi 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Akira Yamamoto 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. Fujitsu Limited

Claims (5)

[Claims] An output stage includes a source follower circuit having a gate and a source of an FET as an input terminal and an output terminal, respectively, a hold capacitor is connected between the gate and a first reference potential, and the gate and a sample are connected. A sample and hold circuit having a first analog switch connected between the input terminal of the hold circuit and a correction capacitor having one end connected to the gate; and a correction capacitor connected between the other end of the correction capacitor and the source. A second analog switch, and a third analog switch connected between the other end of the correction capacitor and a second reference potential. 2. The control circuit according to claim 1, further comprising a control circuit, wherein the control circuit turns on the first analog switch and the second analog switch, turns off the third analog switch, and then controls the first analog switch. And the third analog switch is turned off and the third analog switch is turned on. 3. The control circuit according to claim 1, further comprising: (1) turning on the first analog switch and the second analog switch and turning off the third analog switch; (2) Next, the first analog switch is turned off. (3) Then, the second analog switch is turned off and the third analog switch is turned off.
A sample-and-hold circuit, wherein an analog switch is turned on, and a time from the start of the operation in (2) to the start of the operation in (3) is used as a correction parameter. 4. The liquid crystal display device is provided corresponding to each data electrode, and an output terminal is connected to the data electrode.
4. A data driver, comprising: the sample and hold circuit according to any one of 3 to 3, wherein the FET of the sample and hold circuit is formed of a thin film transistor. 5. A sample and hold circuit according to claim 1, further comprising: a display flat panel in which an output terminal of the sample and hold circuit is connected to a data electrode. Flat panel display.