JPH09320291A - Sample-and-hold circuit and flat panel type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable obtaining high accuracy sample-and-hold voltage, even if a differential amplifier having comparatively high input offset voltage is used, in a sample-and-hold circuit used for a liquid crystal display device and the like. SOLUTION: A switch element 59 is made OFF, a sample-and-hold signal S1 is sampled through a switch element 58, after sample-and-hold signal voltage is held in a capacitor 63, switch elements 59, 60 are made ON, switch elements 61, 62 are made OFF, held voltage in the capacitor 63 is held in a capacitor 64. Next, switch elements 59, 60 are made OFF, switch elements 61, 62 are made ON, and sample-and-hold voltage VB are outputted to an output terminal 66C of an inverted amplifier 66.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit and a flat panel type display device using the same.

[0002]

2. Description of the Related Art FIG. 9 is a circuit diagram conceptually showing an essential part of an example of a conventional liquid crystal display device. In this liquid crystal display device, a data bus driving circuit is formed on a glass substrate forming pixel electrodes forming pixels. A so-called data driver and a scan bus drive circuit, that is, a so-called scan driver are integrally formed.

The actual number of pixels of this liquid crystal display device is 19
20 (horizontal) × 480 (vertical), but in FIG.
For convenience of explanation, the number is 4 (horizontal) × 4 (vertical).

In FIG. 9, 1 is a glass substrate on which pixel electrodes are formed, and 2 is a display portion on which pixels are formed.
_{11-3 44} pixel capacitor comprising a liquid crystal sandwiched between the common electrode and the pixel electrode, 4 _{11-4 44} of N-type which forms a switching element for applying the analog video signal voltage to a corresponding pixel electrode thin film transistors ( Hereinafter referred to as N-type TFT).

Reference numerals 5 _{1 to} 5 ₄ denote a data bus for outputting an analog video signal voltage from a data driver, which will be described later, and 6
_{1-6 4} is a scan bus is output scan signal from the scan driver will be described later.

[0006] 7 is a data driver for driving the data bus 5 ₁ to 5 ₄ outputs an analog video signal voltage to the data bus 5 ₁ to 5 _4, 8 analog video signal and shifts the start pulse SA It is a shift register that sequentially outputs sampling signals D1 to D4.

Further, 9 _{1 to} 9 ₄ are conducted by analog video signal sampling signals D1 to D4, respectively (hereinafter, ON
And an N-type TFT which forms a switching element for analog video signal sampling whose non-conduction (hereinafter referred to as OFF) is controlled.

[0008] In addition, 10 is a scan driver for driving the scan bus 6 _{1-6 4,} 11 is a start pulse S
It is a shift register that shifts B and sequentially outputs scan signals G1 to G4.

FIG. 10 is a timing chart showing the operation of this liquid crystal display device. An analog video signal supplied from the outside and an analog video signal sampling signal D1.
To D4 and scan signals G1 to G4.

That is, in this liquid crystal display device, the first
When the analog video signal of a horizontal line is inputted, the scanning signal G1 is at a high voltage, with N-type TFT 4 ₁₁ to 4 ₁₄ are turned ON at the same time, the analog video signal sampling signal D1~D4 is sequentially to a high voltage , N-type TFT 9 ₁
To 9 ₄ is turned ON in order.

As a result, the analog video signal is an N-type TFT.
The analog video signal voltage is sequentially sampled by 9 _{1 to} 9 ₄ and the analog video signal voltage is held in the data buses 5 _{1 to} 5 ₄ in order, and the analog video signal voltage is written to the pixel capacitors 3 _{11 to} 3 ₁₄ .

In the same manner, the pixel capacitances of the second, third and fourth horizontal lines 3 _{21 to} 3 ₂₄ , 3 _{31 to} 3 ₃₄ , 3 _{41 to} 3 ₄₄ are similarly set.
As for the above, the writing of the analog video signal voltage is sequentially performed, and the display unit 2 displays one screen.

FIG. 11 is a circuit diagram conceptually showing the essential part of another example of a conventional liquid crystal display device. This liquid crystal display device is a data formed by an IC (integrated circuit) made of single crystal silicon. The driver and the scan driver are attached to a panel.

The actual number of pixels of this liquid crystal display device is shown in FIG.
As in the case of the conventional liquid crystal display device shown in FIG.
Although it is (horizontal) × 480 (vertical), in FIG. 11 it is also set to 4 (horizontal) × 4 (vertical) for convenience of explanation.

In FIG. 11, 13 is a glass substrate on which pixel electrodes forming pixels are formed, 14 is a display section on which pixels are formed, and 15 ₁₁ to 15 ₄₄ are sandwiched between the pixel electrode and the common electrode. Pixel capacity consisting of liquid crystal, 16 _{11 to} 16 ₄₄
Is an N-type TFT that forms a switching element for applying an analog video signal voltage to the pixel electrode.

Further, 17 _{1 to} 17 ₄ are data buses to which an analog video signal voltage is output from a data driver described later, and 18 ₁ to 18 ₄ are scan buses to which a scan signal is output from a scan driver described later.

Further, 19 denotes a data bus 17 _{1-17 4} outputs an analog video signal voltage to the data bus 17 _{1-17 4}
Reference numeral 20 is a data driver for driving the shift register, and 20 is a shift register that shifts the start pulse SA and sequentially outputs the analog video signal sampling signals D1 to D4.

Further, 21 _{1 to} 21 ₄ have their sampling operations controlled by the analog video signal sampling signals D1 to D4, respectively, and the sampled and held analog video signal voltage is controlled by the latch enable signal LE so that the data buses 17 _{1 to} 17 _{4 are controlled.} And a sample and hold circuit (SH) that simultaneously outputs to
1 ₁ to 21 ₄ is configured as shown in FIG. 12.

In FIG. 12, 23 ₁ to 23 ₄ are nMOS transistors which are switching elements whose ON / OFF are controlled by analog video signal sampling signals D1 to D4, and 24 _{1 to} 24 ₄ and 25 _{1 to} 25 ₄ are for holding. Is the capacitor.

Further, 26 _{1 to} 26 ₄ and 27 _{1 to} 27 ₄ are voltage follower circuits composed of differential amplifiers 28 _{1 to} 28 ₄ and 29 _{1 to} 29 ₄ , and 30 ₁ to 30 ₄ are latch enable signals L.
It is an nMOS transistor forming a switching element whose ON / OFF is controlled by E.

Further, in FIG. 11, reference numeral 32 designates a scan driver for driving the scan buses 18 ₁ to 18 _4.
3 shifts the start pulse SB and scan signal G1
Is a shift register that sequentially outputs G4 to G4.

FIG. 13 is a timing chart showing the operation of this liquid crystal display device. The analog video signal supplied from the outside and the analog video signal sampling signal D1 are shown.
To D4, the latch enable signal LE, and the scan signals G1 to G4.

That is, in this liquid crystal display device, the first
When the analog video signal of the horizontal line is input, the analog video signal sampling signals D1 to D4 are sequentially set to a high voltage, the nMOS transistors 23 ₁ to 23 ₄ are sequentially turned on, and the analog video signal voltage is changed to the capacitors 24 _{1 to} 24. _Four
Are held in sequence.

Then, when sampling of the analog video signal of the first horizontal line is completed and the horizontal retrace line period starts, the scan signal G1 is set to a high voltage, and the N-type TFTs 16 ₁₁ to 1 are provided.
6 ₁₄ is turned on at the same time, the latch enable signal LE is set to a high voltage, and the N-type TFTs 30 ₁ to 30 ₄ are turned on.
It is said.

[0025] As a result, is held at the same time the capacitor 25 _to 253 ₄ hold voltage of the capacitor 24 _{1-24 4} via the voltage follower circuit 26 ₁ to 26 ₄ and the held voltage to the capacitors 25 _to 253 ₄ However, the voltage follower circuit 2 is used as an analog video signal voltage.
It is simultaneously output to the data buses 17 _{1 to} 17 ₄ via 7 _{1 to} 27 ₄ and written in the pixel capacitors 15 ₁₁ to 15 ₁₄ .

Thereafter, similarly, the pixel capacitances 15 ₂₁ to 15 ₂₄ , 15 ₃₁ to 15 ₃₄ , 1 of the second, third and fourth horizontal lines.
With respect to 5 ₄₁ to 15 ₄₄ as well, the analog video signal voltage is sequentially written, and the display unit 14 displays one screen.

Here, in the conventional liquid crystal display device shown in FIG. 9, the analog video signal voltage is supplied to the data buses 5 _{1 to} 5 _4.
Since the sample-and-hold is directly performed on the data bus, only about 40 ns can be taken as the hold time per data bus, but even in this case, if the size of the panel is relatively small, about 2 inches, It is possible to write the analog video signal voltage to the data buses 5 _{1 to} 5 ₄ within a specified time.

[0028] However, when the size of the panel increases to about 5 inches, the data bus 5 ₁ to 5 ₄ of capacitance and resistance increases, because the time constant of these data buses 5 ₁ to 5 ₄ is increased, defined It becomes impossible to write the analog video signal voltage to the data buses 5 _{1 to} 5 ₄ within the time.

On the other hand, according to the conventional liquid crystal display device shown in FIG. 11, the analog video signal voltage for one horizontal line is simultaneously output from the sample hold circuits 21 _{1 to} 21 ₄ to the data buses 17 _{1 to} 17 ₄ . By doing so, it is possible to use about 1 horizontal period, that is, about 30 μs, as the time for charging one data bus, so that it is possible to drive even a large panel.

[0030]

However, the conventional liquid crystal display device shown in FIG. 11 has a data driver 19 and a scan driver 32 each composed of an IC made of single crystal silicon.
Since it is supposed to be attached to the panel, there was a problem that the price would be high.

On the other hand, in the conventional liquid crystal display device shown in FIG. 9, since the data driver 7 and the scan driver 10 are formed on the glass substrate 1, the liquid crystal display device is lower than the conventional liquid crystal display device shown in FIG. It can be priced.

Therefore, for example, the data driver 19 provided in the conventional liquid crystal display device shown in FIG.
If it can be formed on a glass substrate using T,
It is possible to obtain a liquid crystal display device which can be driven even with a large panel and which is lower in price than the conventional liquid crystal display device shown in FIG.

[0033] Here, as the voltage follower circuit 26 ₁ to 26 _4, 27 ₁ to 27 ₄ constituting the sample-and-hold circuits 21 ₁ to 21 ₄ where data driver 19 is provided, for example, the voltage follower as shown in FIG. 14 It is conceivable to form the circuit on a glass substrate.

In FIG. 14, 35 is a differential amplifier, and 36
Is a non-inverting input terminal, 37 is an inverting input terminal, 38 is an output terminal, 39 to 47 are P-type thin film transistors (hereinafter referred to as P-type TFTs), 48 to 54 are N-type TFTs, 55 is a resistor, 56 is a capacitor, V1 is a DC voltage of 20V.

The P-type TFTs 41 to 43 and the N-type TF
The input differential amplifier is composed of T49 and T50, and is a P-type TFT.
A buffer circuit is composed of 44 to 47 and N-type TFTs 51 to 54, a current mirror circuit is composed of P-type TFTs 39 to 41, 44 and 45, and a current mirror circuit is composed of N-type TFTs 48 and 53.

By the way, since the TFT has a large variation in threshold value and the mobility is varied, the voltage difference between the non-inverting input terminal 36 and the output terminal 38 is varied in the range of about 1 [V]. . This is usually called an input offset voltage.

For example, assuming that the average threshold value of the TFT is 1.5 [V] and only the threshold value of the P-type TFT 43 in the input stage is 0.5 [V], 1 [V]. V] input offset voltage appears.

However, in order to display a high quality image, a differential amplifier having an input offset voltage of several tens of mV or less is required, and a differential amplifier having an input offset voltage of 1 [V] is used in FIG. If a data driver 19 as provided in the conventional liquid crystal display device shown in the above is formed on a glass substrate, a good quality image cannot be obtained. Since the input offset voltage of the differential amplifier made of the single crystal silicon IC is several tens of mV or less, such a problem does not occur.

In view of the above points, the present invention provides a sample hold circuit capable of obtaining a highly accurate sample hold voltage as an output voltage even when a differential amplifier having a relatively large input offset voltage is used. To provide a flat panel type display device whose first purpose is to provide a high quality image and to reduce the cost even when a relatively large panel is used. The second purpose is to provide.

[0040]

FIG. 1 is a principle circuit diagram of a sample hold circuit (sample hold circuit according to claim 1) of the first invention in the present invention. In FIG. 1, S1 is a sampled and held signal to be sampled and held,
VB is a sample and hold voltage output from the sample and hold circuit of the first invention.

Further, 58 to 62 are switch elements, 63,
64 is a holding capacitor, 65 is a differential amplifier, 6
Reference numeral 6 is an inverting amplifier. The switch element 61 may not be provided.

Here, the switch element 58 has one end 58A.
The sample-and-hold signal S1 is applied to the capacitor 63. The capacitor 63 has one end 63A connected to the other end 58B of the switch element 58 and the other end 63B grounded.

The switch element 59 has one end 59A connected to one end 63A of the capacitor 63, and is connected to the differential amplifier 6
5 is a non-inverting input terminal of the other end 59B of the switch element 59
It is connected to the.

The switch element 60 has one end 60A connected to the output terminal of the differential amplifier 65 and the other end 60B connected to the inverting input terminal of the differential amplifier 65, and the capacitor 64 switches one end 64A. The other end 60 of the element 60
The other end 64B is grounded.

The switch element 61 has one end 61A connected to the output terminal of the differential amplifier 65, and the inverting amplifier 66 has one input end 66A connected to the other end 61B of the switch element 61 and the other end. The input end 66B is connected to one end 64A of the capacitor 64.

The inverting amplifier 66 is for inverting and amplifying the voltage difference between the voltage applied to the input terminal 66A and the voltage applied to the input terminal 66B. For example, the differential amplifier 67 and the resistors 68 and 69. It can be composed of and.

The switch element 62 has one end 62A connected to the output end 66C of the inverting amplifier 66 and the other end 62B.
Is connected to the non-inverting input terminal of the differential amplifier 65.

When the sample-hold signal S1 is sampled and held, the switch element 5 is used.
After turning off 9 and sampling the sample-hold signal S1 via the switch element 58, the switch elements 59 and 60 are turned on, the switch elements 61 and 62 are turned off, and the hold voltage of the capacitor 63 is held in the capacitor 64. The switch elements 59 and 60 are turned off, the switch elements 61 and 62 are turned on, and the sample hold voltage VB is output to the output terminal 66C of the inverting amplifier 66.

In the sample and hold circuit of the first invention, the output voltage of the differential amplifier 65 and the capacitor 6
The voltage difference from the hold voltage of 4 is the input offset voltage of the inverting amplifier 66 divided by the amplification degree of the differential amplifier 65.
Even if the input offset voltage of the differential amplifier 65 is large, a highly accurate sample hold voltage can be obtained as the output voltage.

Further, in the present invention, the sample and hold circuit of the second invention (the sample and hold circuit according to claim 2).
In the sample hold circuit of the first aspect of the invention, the switch elements 58 to 62 are analog switches made of thin film transistors, and the transistors forming the differential amplifier 65 and the inverting amplifier 66 are thin film transistors.

The sample and hold circuit of the second invention can be formed, for example, on a transparent substrate which constitutes a flat panel type display device, and in the case of such a constitution, the differential amplifier 65 Although the input offset voltage becomes large, the sample-hold voltage VB with high accuracy can be obtained as the output voltage.

Further, the flat panel type display device of the present invention (the flat panel type display device according to claim 3) forms a plurality of data buses for supplying an analog video signal voltage to the pixel electrodes forming the pixels. And a data driver having a plurality of sample and hold circuits that simultaneously output an analog video signal voltage obtained by sample-holding an analog video signal supplied from the outside to a plurality of data buses. In, the plurality of sample and hold circuits are configured by the sample and hold circuit of the second invention, and the data driver is formed on the transparent substrate.

Since the flat panel type display device of the present invention is provided with the data driver for simultaneously outputting the analog video signal voltage to the plurality of data buses, even if a relatively large panel is used, the data bus is not used. Since sufficient time can be taken for charging and a plurality of sample and hold circuits are configured by the sample and hold circuit of the second invention, it is possible to supply a highly accurate analog video signal voltage to the data bus. It is possible to display a high quality image.

A plurality of sample and hold circuits are provided in the second
Since the sample-and-hold circuit of the present invention is used and the data driver is formed on the transparent substrate, the cost can be reduced.

[0055]

BEST MODE FOR CARRYING OUT THE INVENTION One Embodiment of a Sample and Hold Circuit of the Present Invention FIGS. 2 to 6 FIG. 2 is a circuit diagram showing one embodiment of a sample and hold circuit of the present invention together with a load. In FIG. 2, reference numeral 75 is an embodiment of the sample and hold circuit of the present invention, 76 is an input terminal to which a sample and hold signal S4 to be sampled and held is applied, and 77 is a sample and hold voltage output terminal. It is an output terminal.

Reference numerals 78 to 83 are analog switches. In the analog switch 78, 84 is a P-type TFT whose ON / OFF is controlled by a control signal / S5,
Reference numeral 85 is an N-type TFT whose ON / OFF is controlled by a control signal S5 having an inverted relationship with the control signal / S5.

Further, in the analog switches 79 and 80, 86 and 87 are turned on and off by the control signal / S6.
P-type TFT, 88 and 89 are controlled by the control signal / S6
Is an N-type TFT whose ON / OFF is controlled by a control signal S6 having an inversion relation with.

In the analog switches 81-83, 90-92 are P-type TFTs whose ON / OFF is controlled by the control signal S6, and 93-95 N-types whose ON / OFF is controlled by the control signal / S6. It is a TFT.

Further, 96 and 97 are capacitors for holding, 98 and 99 are differential amplifiers having transistors as TFTs, 100 and 101 are resistors, and 102 is a load of one embodiment of the sample and hold circuit of the present invention. 103 is a DC voltage source.

FIG. 3 is a circuit diagram showing the structure of the differential amplifier 98. In FIG. 3, 105 is a non-inverting input terminal, 106 is an inverting input terminal, 107 is an output terminal, 108 to 113 are P-type TFTs, 114 to 117 are N-type TFTs, 118 is a resistor,
Reference numeral 119 is a capacitor, and V2 is a DC voltage of 20V.

It should be noted that the P-type TFTs 110 to 112 and the N-type TFTs 115 and 116 form an input differential amplifier.
The type TFT 113 and the N type TFT 117 form an output buffer circuit, and the P type TFTs 108 to 110 and 113 form a current mirror circuit.

FIG. 4 is a circuit diagram showing the structure of the differential amplifier 99. In FIG. 4, 121 is a non-inverting input terminal, 12
2 is an inverting input terminal, 123 is an output terminal, and 124 to 132
Is a P-type TFT, 133 to 139 is an N-type TFT, 140 is a resistor, 141 is a capacitor, and V3 is a DC voltage of 20V.

It should be noted that the P-type TFTs 126 to 128 and the N-type TFTs 134 and 135 form an input differential amplifier.
Type TFTs 129 to 132 and N type TFTs 136 to 139
The output buffer circuit is composed of the P-type TFTs 124-1.
26, 129, and 130 form a current mirror circuit, and N-type TFTs 133 and 138 form a current mirror circuit.

Here, in the seventy-fifth embodiment of the sample and hold circuit of the present invention, when sampling and holding the sampled and held signal S4, first, the control signal S5 = 0 [V] and the control signal / S5 = 20 [V], control signal S6 = 0 [V], control signal / S6 = 20 [V], analog switches 78-80 = OFF, and analog switches 81-83 = ON.

Control signal S5 = 20 [V], control signal / S5 = 0 [V], analog switch 78 = ON
The sampled and held signal S4 is sampled by the analog switch 78 and the sampled and held signal voltage is held in the capacitor 96, and then the control signal S5 = 0 [V], the control signal / S5 = 20 [V], The analog switch 78 is turned off.

Next, control signal S6 = 20 [V], control signal / S6 = 0 [V], analog switches 79, 80 =
ON, analog switches 81 to 83 = OFF.

In this case, since the voltage follower circuit is composed of the differential amplifier 98 and the analog switch 80, the hold voltage of the capacitor 96 is set to the differential amplifier 98.
The voltage is held in the capacitor 97 via a voltage follower circuit composed of the analog switch 80 and the analog switch 80.

Then, control signal S6 = 0 [V], control signal / S6 = 20 [V], analog switches 79 and 80
= OFF, analog switches 81 to 83 = ON, and the sample hold voltage is output to the output terminal 77.

Here, the sampled and held signal voltage at the time of sampling is 13 [V], and as shown by the DC voltage sources 143 and 144 in FIG. 5, the differential amplifier 98 sets the input offset voltage ΔV98 to 1 [V]. ], And the differential amplifier 99 sets the input offset voltage ΔV99 to 0.
Suppose that it has 5 [V].

When the analog switch 78 is turned ON and the sampled and held signal S4 is sampled, the hold voltage of the capacitor 96 is ideally 13 [V].

After that, analog switches 79, 80 =
When turned on, the hold voltage of the capacitor 96 is held in the capacitor 97 via the voltage follower circuit composed of the differential amplifier 98 and the analog switch 80.
6 hold voltage-input offset voltage of differential amplifier 98 ΔV98 = 13-1 = 12 [V].

That is, in the differential amplifier 98, when the analog switch 80 is turned off, the voltage of its inverting input terminal is 13 [V] and its inverting input terminal is 12 [V].
In this case, it can be said that the voltage at the output terminal is stable at 12 [V].

Then, the analog switches 79 and 80 =
When OFF and analog switches 81 to 83 = ON, the differential amplifier 98 operates as a comparator, and the differential amplifier 99 operates as an inverting amplifier with the resistors 100 and 101. The output of the amplifier 99 is
It is fed back to the inverted input terminal of the differential amplifier 98.

In this case, the voltage at the inverting input terminal of the differential amplifier 98 is maintained at 12 [V] by the capacitor 97, but this differential amplifier 98 has its inverting input terminal at the inverted input terminal as described above. When the voltage is 13 [V] and the voltage at the inverting input terminal is 12 [V], the voltage at the output terminal is stable at 12 [V].

As a result, if the output voltage of the differential amplifier 99 becomes lower than 13 [V], the differential amplifier 98
Since a voltage obtained by multiplying the voltage difference from 13 [V] by the amplification degree is output, the output voltage of the differential amplifier 98 rapidly becomes a voltage lower than 12 [V], and the output voltage of the differential amplifier 99 is increased. The output voltage rapidly returns to 13 [V].

On the other hand, when the output voltage of the differential amplifier 99 becomes higher than 13 [V], the differential amplifier 98 outputs a voltage obtained by multiplying the voltage difference with 13 [V] by the amplification degree. Therefore, the output of the differential amplifier 98 rapidly becomes 1
The voltage becomes higher than 2 [V], and the output of the differential amplifier 99 rapidly tries to return to 13 [V].

That is, in the case of this example, the circuit becomes stable when the voltage of the output terminal 77 becomes 13 [V] which is the same voltage as the voltage held in the capacitor 96 at the time of sampling.

Strictly speaking, since the input offset voltage ΔV99 of the differential amplifier 99 is 0.5 [V], assuming that the amplification degree of the differential amplifier 98 is A98, the input to the inverted input terminal of the differential amplifier 98 is input. The voltage is (13-0.5 / A98)
In the case of [V], the output of the differential amplifier 98 is 11.5.
[V], and the input offset voltage Δ of the differential amplifier 99
The circuit becomes stable by canceling V99.

Here, the differential amplifier 98 has its amplification degree A
98 is designed several hundred times,
Even if it is assumed to be 0 times smaller, the difference of the output voltage of the differential amplifier 99 from 13 [V] is 0.005 [V].

That is, in the 75th embodiment of the sample and hold circuit of the present invention, the difference between the sampled and held signal voltage and the voltage output to the output terminal 77 is ΔV99 /
It becomes extremely small as A98.

By the way, FIG. 6 shows a simulation result when the sample-hold operation is repeated with the sample-hold signal voltage being 13 [V] and 30 μs being one cycle. The control signals S5 and S6 and the capacitor 96 are shown in FIG. , 97, and the hold voltage of the load 102.

This simulation is based on the assumption that the embodiment 75 of the sample hold circuit of the present invention is used for the data driver of the liquid crystal display device, and it is 30 μs.
Is about 1 horizontal period, the high voltage period of the control signal S5 is a period allowed when sampling an analog video signal, and the load 102 has a capacity per data bus,
The voltage from the DC voltage source 103 is assumed to be a common voltage.

According to this example, the hold voltage of the capacitor 96 slightly changes to 12.984 [V] due to the gate-source capacitance and the gate-drain capacitance of the P-type TFT 84 and the N-type TFT 85. There is.

The hold voltage of the capacitor 97 is
The input offset voltage ΔV98 of the differential amplifier 98 is 1
Since it is [V], it is reduced by about 1 [V] to 11.991.
Although it is [V], the hold voltage of the load 102 is
It is stable at 12.982 [V].

As described above, according to the seventy-fifth embodiment of the sample and hold circuit of the present invention, even when the differential amplifiers 98 and 99 having a relatively large input offset voltage are used, a sample having a high accuracy as an output voltage is used. Hold voltage can be obtained.

In the sample and hold circuit according to the seventy-fifth embodiment of the present invention, the transistor is formed of a TFT, and therefore, the sample and hold which constitutes the data driver is formed on the glass substrate which forms the pixel electrode which constitutes the liquid crystal display device. It can be formed as a circuit, and in this case, even when using a relatively large panel,
It is possible to obtain a liquid crystal display device that can display a high-quality image at a low price.

Embodiment of Flat Panel Display Device of the Present Invention FIG. 7, FIG. 8 FIG. 7 is a conceptual view of a main part of a liquid crystal display device which is an embodiment of a flat panel display device of the present invention. 9 is a circuit diagram shown in FIG. 9. In this embodiment, a data driver 146 having a circuit configuration different from that of the data driver 7 provided in the conventional liquid crystal display device shown in FIG. 9 is formed on the glass substrate 1. It has the same structure as the conventional liquid crystal display device shown in FIG.

In the data driver 146, 147 is a shift register that shifts the start pulse SA and sequentially outputs the analog video signal sampling signals D1, / D1 to D4, / D4, and 148 _{1 to} 148 ₄ are the present invention shown in FIG. This is a sample and hold circuit having the same configuration as that of Embodiment 75 of the above sample and hold circuit.

The sample and hold circuit 148 ₁ is supplied with the analog video signal sampling signals D1 and / D1 as the control signals S5 and / S5, and the sample and hold circuit 148 ₂ is supplied with the analog video signal sampling signals as the control signals S5 and / S5. The signals D2 and / D2 are supplied.

Further, the sample and hold circuit 148 ₃ is supplied with the analog video signal sampling signals D3 and / D3 as the control signals S5 and / S5, and the sample and hold circuit 148 ₄ is supplied with the control signals S4 and / S4.
Analog video signal sampling signal D4, / D4
Is supplied.

Further, these sample hold circuits 148
In _{1-148 4,} the control signal S6, / S6 as a latch enable signal LE, / LE is supplied.

FIG. 8 is a timing chart showing the operation of the liquid crystal display device which is one embodiment of the flat panel type display device of the present invention. The analog video signal supplied from the outside and the analog video signal sampling signal D2. , Latch enable signals LE, / LE, the output of the sample hold circuit 148 ₂ , and the scan signals G1, G2, G3.
Are shown.

That is, in the liquid crystal display device which is one embodiment of the flat panel type display device of the present invention, the latch enable signal LE = 0 [V] and the latch enable signal / LE = 20 [V] are set, and the sample Hold circuit 14
8 ₁ in to 148 _4, analog switches 79,8
Analog switch corresponding to 0 = OFF, analog
Analog switch corresponding to switches 81 to 83 = O
In the state of N, the analog video signal of the first horizontal line is input.

Then, the analog video signal sampling signals D1 to D4 are sequentially changed to 0 [V] → 20 [V] → 0 [V], and the analog video signal sampling signal / D is generated.
1 to / D4 are sequentially set to 20 [V] → 0 [V] → 20 [V].

As a result, the sample hold circuit 148 ₁
In to 148 _4, the analog switches are sequentially set to OFF → ON → OFF corresponding to the analog switch 78, the analog video signal is sampled, the analog video signal voltage is held in the capacitor corresponding to the capacitor 96.

Then, during the horizontal blanking period, the latch enable signal LE = 20 [V] and the latch enable signal / L
E = 0 [V], analog switches corresponding to the analog switches 79 and 80 = ON, and analog switches corresponding to the analog switches 81 to 83 = OFF.

As a result, the holding voltage of the capacitor corresponding to the capacitor 96 is
The voltage is held by the capacitor corresponding to the capacitor 97 via the voltage follower circuit corresponding to the voltage follower circuit configured by the switch 80.

Similarly, during the horizontal blanking period, the latch enable signal LE = 0 [V] and the latch enable signal / LE = 20 [V] are set, and the analog switch 7
The analog switches corresponding to 9 and 80 = OFF, and the analog switches corresponding to the analog switches 81 to 83 = ON.

As a result, the sample hold circuit 148 ₁
Analog video signal voltage sampled and held from to 148 ₄ are outputted simultaneously to the data bus 5 ₁ to 5 _4, data buses 5 ₁ to 5 ₄ are charged.

Then, at the same time when the analog video signal of the second horizontal line is input from the outside, the scan signal G1 is set to a high voltage, the N-type TFTs 4 ₁₁ to 4 ₁₄ = ON, and the data buses 5 _{1 to} 5 _{4 are} turned on. The analog video signal voltage held by is written in the pixel capacitors 3 _{11 to} 3 ₁₄ .

Similarly, the pixel capacitances of the second, third, and fourth horizontal lines 3 _{21 to} 3 ₂₄ , 3 _{31 to} 3 ₃₄ , 3 _{41 to} 3 ₄₄ are similarly set.
As for the above, the writing of the analog video signal voltage is sequentially performed, and the display unit 2 displays one screen.

As described above, according to the liquid crystal display device of the embodiment of the flat panel type display device of the present invention, the analog video signal voltage for one horizontal line is simultaneously output from the sample hold circuits 148 _{1 to} 148 ₄ to the data bus 5. because it is to output to _{1-5 4,} one horizontal period of about a time for charging a one per data bus, i.e., about 30μs
Can be used, the data buses 5 _{1 to} 5 ₄ can be sufficiently driven and the sample hold circuits 148 ₁ to ₁ 48 ₁ can be used even when the panel is relatively large.
As the sample-hold circuit having the same structure as that of the sample-hold circuit 75 according to the embodiment 75 of the present invention shown in FIG. 2 as 48 ₈ , a highly accurate analog video signal voltage is supplied to the data buses 5 _{1 to} 5 ₄ . It is possible to display a high quality image.

Further, the sample hold circuits 148 ₁ to 1
Since the data driver 146 formed by using the sample-and-hold circuit of one embodiment 75 of the same configuration of the embodiment of the sample hold circuit of the present invention shown as 48 ₈ in FIG. 2 are formed on the glass substrate 1, shown in FIG. 11 The price can be lower than that of the conventional liquid crystal display device.

[0104]

According to the sample and hold circuit of the first invention (the sample and hold circuit according to the first aspect) of the present invention, the output voltage is increased even when a differential amplifier having a relatively large input offset voltage is used. As a result, a highly accurate sample hold voltage can be obtained.

Further, in the present invention, according to the sample hold circuit of the second invention (sample hold circuit according to claim 2), it can be formed, for example, on a transparent substrate which constitutes a flat panel type display device. Also, in this case, although the input offset voltage of the differential amplifier becomes large, a highly accurate sample hold voltage can be obtained as the output voltage.

Further, according to the flat panel display device of the present invention (the flat panel display device according to claim 3), it is possible to display a good quality image even when a relatively large panel is used. At the same time, the price can be reduced.

[Brief description of drawings]

FIG. 1 is a principle circuit diagram of a sample and hold circuit of a first invention in the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a sample hold circuit of the present invention together with a load.

FIG. 3 is a circuit diagram showing a configuration of a differential amplifier at a preceding stage included in an embodiment of the sample hold circuit of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a differential amplifier at a subsequent stage included in one embodiment of the sample hold circuit of the present invention.

FIG. 5 is a circuit diagram showing an input offset voltage included in a differential amplifier included in an embodiment of the sample hold circuit of the present invention.

FIG. 6 is a timing chart showing a simulation result of an operation example of the embodiment of the sample hold circuit of the present invention.

FIG. 7 is a circuit diagram conceptually showing a main part of a liquid crystal display device which is an embodiment of a flat panel display device of the present invention.

FIG. 8 is a timing chart showing the operation of the liquid crystal display device of the liquid crystal display device which is an embodiment of the flat panel display device of the present invention.

FIG. 9 is a circuit diagram conceptually showing a main part of an example of a conventional liquid crystal display device.

10 is a timing chart showing an operation of the conventional liquid crystal display device shown in FIG.

FIG. 11 is a circuit diagram conceptually showing a main part of another example of a conventional liquid crystal display device.

12 is a circuit diagram showing a configuration of a sample hold circuit included in the conventional liquid crystal display device shown in FIG.

13 is a timing chart showing an operation of the conventional liquid crystal display device shown in FIG.

FIG. 14 is a circuit diagram showing an example of a voltage follower circuit.

[Explanation of symbols]

S1 sample-and-hold signal S4 sample-and-hold signal S5, / S5, S6, / S6 control signal D1, / D1 to D4, / D4 analog video signal sampling signal

Front page continued (72) Inventor Kenichi Nakabayashi 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Mitsuharu Nakazawa 4-1-1, Kamedotachu, Nakahara-ku, Kawasaki-shi, Kanagawa Issue within Fujitsu Limited

Claims (3)

[Claims] 1. A first capacitor (63) to which a sample-and-hold signal (S1) is applied via a first switching element (58) and an output terminal via a second switching element (60). A differential amplifier (65) connected to the inverting input terminal, to which the hold voltage of the first capacitor (63) is applied to the non-inverting input terminal via the third switch element (59), and one end (64A) Is connected to the inverting input terminal of the differential amplifier (65), the other end (64B) is grounded to the second capacitor (64), and the output end (66C) is connected via the fourth switch element (62). Connected to the non-inverting input terminal of the differential amplifier (65A), the voltage difference between the output voltage of the differential amplifier (65) and the voltage of one end (64A) of the second capacitor (64) is inverted and amplified. With an inverting amplifier (66) The third switch element (59) is made non-conductive, the sampled and held signal is sampled through the first switch element (58), and then the second and third switch elements (60, 59). Conduction,
The fourth switch element (62) is made non-conducting, the hold voltage of the first capacitor (63) is held in the second capacitor (64), and then the second and third switch elements are held. (60, 59) is non-conductive, the fourth switch element (62) is conductive,
A sample hold circuit controlled to output a sample hold voltage (VB) to an output terminal (66C) of the inverting amplifier (66). 2. The first to fourth switch elements (58, 6)
0, 59, 62) is an analog switch composed of thin film transistors, and the transistors composing the differential amplifier (65) and the inverting amplifier (66) are composed of thin film transistors. The sample hold circuit according to item 1. 3. A transparent substrate having a plurality of data buses for supplying analog video signal voltage to pixel electrodes forming pixels, and an analog video signal voltage obtained by sampling and holding an analog video signal supplied from the outside. And a data driver having a plurality of sample and hold circuits for simultaneously outputting the plurality of sample and hold circuits to the plurality of data buses, wherein the plurality of sample and hold circuits are configured by the sample and hold circuits according to claim 2. A flat panel type display device, wherein the data driver is formed on the transparent substrate.