SU1156064A1 - Multiplying device - Google Patents

Abstract

A device Gsch containing a matrix of elements And and a matrix of one-digit adders, with the first inputs of the elements and; matrix column

Description

the fourth And elements, the input of the delay element is connected to the first control input of the one-bit adder and the first inputs of the fifth and ninth And elements, the output of the delay element is connected to the input of the fourth element NOT, the output of which is connected to the fourth inputs of the And elements from the first to the fourth and fourth with the third inputs of the elements I from the sixth to the eighth, the second inputs of the fifth and the ninth elements And are connected to the second control input of the one-bit adder, the third inputs of the fifth and ninth elements And are connected to the outputs of the corresponding venno first and second OR elements, the first control inputs

6064

single-digit adders of the pth and 2p-th rows of the matrix are connected respectively to the first and second clock inputs of the device, the second control inputs of the one-bit adders of the pth and 2p-th rows of the matrix are connected respectively to the first and second inputs of the device reset, transfer outputs one-digit adders of the 2p-th row of the matrix are connected to the second information inputs of the corresponding one-digit adders of the first row of the matrix, the outputs of the one-bit adders from the second to the n-and twop-row of the matrix are connected to the third inputs of norazr dnyh adders respectively the first to (n-1) row -ipervoy matrix.

The invention relates to digital computing and is intended for use in universal and specialized digital computing devices. The purpose of the invention is to reduce hardware costs when implementing a matrix multiplier. Fig. 1 shows the functional scheme of the proposed multiplication device (for); in fig. 2 - the same, one-bit adder of the first and third rows of the matrix; in fig. 3 - the same, one-bit adder of the second and fourth term of the matrix; in fig. 4 - time diagram of the device. The device contains a matrix of one-bit adders 1.1-1, And. 2.1-2.I, 3.1-Z.p, 4.1-4.P, matrix of elements And 5, inputs 6.1-6, n bits of the first operand A, inputs 7.1-7.4 bits of the second operand B clock inputs 8.1-8.2, inputs 9.1 and 9.2 of reset, outputs 10.1-10.4 of the product C, additional inputs 11. The adder 1.1 (3.i) contains the elements NOT 12, AND 13 and OR 14. The adder 2.1 (4.i) contains the element NOT 15, AND 16, OR 17 and delays 18. The device operates in a conveyor mode, the essence of which is as follows. In the initial state, inputs 8.1, 8.2, 9.1, and 9.2 are set to signal 1. Before the multiplier begins operation, a negative pulse is applied to input 9.2, which resets the one-bit adders 4.1-4, n to the zero state, while The four outputs of the sum and the transfer set the signal O. The calculation process begins with the input to the inputs 6.1,,. ,, 6.A, -discharge binary multiplier A and the two least significant bits Bf, B and - the bit multiplier IB to the inputs 7.1 and 7.2. Through time T, input 8.1 is given a signal O, which is summed on adders 2.1-2. And that xi 5 where, J /, - the maximum time of the transition process in the logical element And; The value is determined by the inequality nSixMEP "P-mo., - (), (Tde E - the time delay of the signal in the delay element;,. With 0-. The maximum and the current transition time in the logical element .NE at the transition, respectively, from 1 O and from O to U and from u, in g O is the minimum and the maximum delay time of the signal at one bit for the full adder when passing the signals from the inputs to the outputs (in all full one-bit digits pax it is the same). (mot, since the calculations in the first two lines have ended, input 8.1 is fed signal 1, which memorizes information established at the outputs of adders 2.1-2.h, and prohibits the adders to work out 2.1-2.h signals that appear at their information inputs. During the time that ia adders 1.1 are being calculated -ln and 2.1-2.M, on the adders 3.1-Z.p and 4.1-4. The preparatory process is underway and the calculation at the inputs 7.3-7.4 is applied to bits B and B of the multiplier B, the feed is completed to the moment (s) B and B, the calculation continues on the adders 3.1-З.п, and then after applying through time (that w + ak to the input 8.2 of the signal O and to the adder x 4.1-4..VI. At the same time on adders 1. 1 -1. H and G2,1-2. And the two lower bits, C and C, of the product are read.

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 - maximum time; 64 .4 C from outputs 10.1 and 10.2, as well as the filing of bits B and B of multiplier B pa inputs 7.1,7.2. After filing at the time point (+ 2P moix ° signal 1, which performs the t-commemoration of the intermediate result - on the outputs of adders 4.1-4.f, as well as the prohibition of working on adders 4.1-4.1 of the incoming information, the calculation continues to accumulators 1.1-1. fl and 2.1-2. P. During the time, while there are 1adti calculations, reading of bits C, C of the product, C from the outputs of the multiplier 10.3 and 10.4 and supplying the bits By and Eg of the multiplier B to the inputs 7.3 and 7.4. The process continues cyclically. When all n bits of the multiplier B are submitted, the inputs .1–7.4 are set There is a signal O, and the calculation process does not stop until all 2 n product bits C are obtained from outputs 10.1-10.4. If it is necessary to accelerate the results, you can finish the calculation as soon as you enter bits B ,,, and B multiplier and summing them Then, at the outputs of the sum and carry of adders 4.14 .11, a two-bit code of higher bits of product C will be obtained, which, after summing up on an accelerator of the adder, will give the value of the higher bits of product C. For ozhitel, maximum performance, and also for enabling read and switching intermediate information bits in the multiplier value R should be determined based on the following inequality skste1 claim 1

necessary to read the result from the outputs 10.1-10.4 multiplier;

t t. - max and min if ii

the minimum switching time of the bits of the multiplier B at inputs 7.1-7.4, taking into account the time of passage of signals through the elements of AND 5;

cddh 1 - value equal to the larger of the elements written in square brackets.

The presence in the device inputs 1 Kil. 4 allows to increase the discharge. This is convenient for modular implementation of a) and multiplier or in the form of an integrated circuit, while increasing the bit is achieved by appropriate switching of inputs 11.1-11.4 of one module with outputs 10.1-10.4 of another module.

The proposed device can multiply not only two-bit numbers, it allows you to multiply n-bit by the number of any finite bit size m, and only the number of work cycles changes.

tS The presence of two inputs 9.1 and 9.2 allows a more efficient use of the multiplier at different Ti i points.

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Claims (1)

(.57) A DEVICE FOR MULTIPLICATION, containing a matrix of elements AND and a matrix of one-bit adders, the first inputs of the elements of the I1th column of the matrix (<= 1, ..., in; P is the number of bits of the first operand) are connected to the input of the corresponding bit of the first operand of the device, the second inputs of the elements of the Ith row of the matrix (j = 1, ..., 2p; P is an arbitrary integer) are connected to the corresponding input of the job of the second operand of the device , the outputs of the elements And the ith row of the matrix are connected to. the first information inputs of the corresponding one-bit adders of the corresponding row of the matrix, the transfer output of each one-bit adder of the 1st column of the matrix is connected to the second information input of the subsequent one-bit adder of the same column of the matrix, the output of the sum of the 1st single-bit adder of the Jth row of the matrix is connected to the third information input Of the (1-1) -th single-bit adder of the (j + 1) -th row of the matrix, the outputs of the sum of the single-bit adders of the first column of the matrix are the outputs of the device, distinguishing its purpose is that, in order to simplify the device, each single-bit adder of the ρ-th and 2-nd rows of the matrix contains nine AND elements, two OR elements, four NOT elements and a delay element, and the outputs of the first and fifth elements AND are connected to the inputs of the first the OR element, the output of which is connected to the output of the sum of a single-bit adder, the outputs of the AND elements from the sixth to the ninth are connected to the inputs of the second OR element, the output of which is connected to the transfer output of the single-bit adder. the input of the first element is NOT connected to. the first information input of the one-bit adder and the first inputs of the first, fourth, seventh and eighth elements AND, the output of the first element is NOT connected to the first inputs of the second and third elements AND, the input of the second element is NOT connected to the second information input of the one-bit adder, second inputs of the first, third and the eighth element AND and the first input of the sixth element AND, the output of the second element is NOT connected to the second inputs of the second and fourth elements AND, the input of the third element is NOT connected to the third m input single-digit adder, the second inputs of the sixth and seventh elements And and with the third inputs of the first and second elements And, the output of the third element is NOT connected to the third inputs of the third and fourth elements AND, the input of the delay element is connected to the first control input of the single-bit adder and the first inputs of the fifth and ninth elements AND, the output of the delay element is connected to the input of the fourth element NOT, the output of which is connected to the fourth inputs of the elements And from the first to fourth and with the third inputs of the elements And from the sixth to the eighth, the second inputs of the fifth and ninth elements And are connected to the second control input of a single-bit adder, the third the inputs of the fifth and ninth AND elements are connected to the outputs of the first and second OR elements, respectively, the first control inputs of the single-bit adders of the rth and 2nd pth rows of the matrix are connected respectively to the first and second clock inputs of the device, the second control inputs of the single-bit adders -th matrix rows are connected respectively to the first and second inputs of the device reset, the transfer outputs of single-digit adders of the 2nd matrix row are connected to the second information inputs of the corresponding single-bit sums tori of the first row of the matrix, the outputs of the one-bit adders from the second to the pth and 2nd pth rows of the matrix are connected to the third inputs of the single-bit adders, respectively, from the first to the (p-1) -th first row of the matrix.