SU1005317A1

SU1005317A1 - Threshold logic element

Info

Publication number: SU1005317A1
Application number: SU813331407A
Authority: SU
Inventors: Олег Николаевич Музыченко
Original assignee: Войсковая часть 31303
Priority date: 1981-04-28
Filing date: 1981-04-28
Publication date: 1983-03-15

Description

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Изобретение относитс к автомати-i ке и вычислительной технике и может быть исполь зовано дл построени различных устройств переработки дискретной информации.The invention relates to automation and computing and can be used to build various devices for processing discrete information.

Известен пороговый логический элемент , содержащий многовходовый элемент ИЛИ, входыкоторого соединены с выходами п ти трехвходовых элементов И, две группы по четыре двухвходовых элемента ИЛИ, соединенных со входами элементов И 1 .A threshold logic element is known, containing a multi-input element OR, whose inputs are connected to the outputs of five three-input elements AND, two groups of four two-input elements OR, connected to the inputs of elements AND 1.

Недостатком данного элемента вл етс ограниченные функциональные -ВОЗМОЖНОСТИ, так какон реализуеу только пороговую функцию семи переменных с порогом 3.The disadvantage of this element is limited functional -POSSIBILITIES, since it implements only the threshold function of seven variables with a threshold of 3.

Известен также мажоритарный логический элемент, содержащий преобразователи весов двух входов, состо щие из элемента И и элемента ИЛИ с параллельно соединенными входами, блок формировани порога и выходной ИЛИ. Блок формировани порогаAlso known is the majority logic element, which contains the transducers of the weights of the two inputs, consisting of the AND element and the OR element with the inputs connected in parallel, the threshold generation unit and the output OR. Threshold Forming Unit

выполнен двухступенчатым, содержащим два однотипных каскада формировани наЬора весов первой ступени, взаимодополн ющие весовые выходы которых попарно соединены со входами элементов И каскада формировани порога второй ступени f23.performed in two stages, containing two single-type cascades of formation of a set of scales of the first stage, the complementary weight outputs of which are pairwise connected to the inputs of the elements of the cascade of forming the threshold of the second stage f23.

Недостатком таких устройств вл етс малые функциональные возможности .The disadvantage of such devices is low functionality.

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Наиболее близким по технической сущности к изобретению вл етс пороговый логический элемент, содержащий К столбцов сумматоров, входы сумматоров первого столбца из которых под15 ключены к одним шинам входных сигналов Г 3 .The closest in technical essence to the invention is a threshold logic element containing K columns of adders, the inputs of the adders of the first column of which are connected to one bus of the input signals of G 3.

Недостатками такого устройства вл ютс сложность технической реализации , малые функциональные возмож20 ности и быстродействие. ;The disadvantages of such a device are the complexity of the technical implementation, low functionality and speed. ;

Цель изобретени - повышение быстродействи и расширение функциональ .ных возможностей. 3 Дл достижени поставленной цели в пороговый логический элемент, содержащий К столбцов сумматоров, вхо ды сумматоров первого столбца подкл чены к шинам входных сигналов, введен элемент ИЛИ, выход которого под ключен к шине выходных сигналов, а входы - к выходам переноса сумматоров (столбцов от Р-гр до К-го, дл порога 2Р, выходы каждого из сумматоров столбцов от первого до (P-l)подключены к входам одного из сумма торов последующих столбцов, а выход суммы каждого из сумматоров остальных столбцов подключены к входам од ного из сумматоров последующих стол цов, при этом входы переноса сумматоров всех столбцов подключены к шинам входных сигналов. На чертеже изображен предлагаемы пороговый логический элемент дл случа , числа входов равных тридцати одному и порога . Предлагаемый пороговый элемент дл случа числа входов равных трид цати одному состоит из сумматоров 1-1-1-8, входы которых подключены к входным шинам порогового логического элемента, сумматоров , 3-1, И k двухразр дных двоичных чисел, и элемента ИЛИ 5, а также входов 6-36. Выходы каждых двух сумматоров 1 соединены со входами соответствующего сумматора 2, вход переноса которого соединен с входом порогового элемента. Выходы суммы сумматоров 2-1 и 2-2 соединены со входами сумматора , а выходы суммы сумматоров 2-3 и 2-k - с входами сумматора 3-2. Входы переноса сумматоров и соединены со входами порогового логического элемента. Выходы суммы сумматоров и соединены со входами последнего сумматора k, вход переноса которого соединен со входом -порогового логического элемен та. Выходы переноса всех сумматоров Р-разр дных двоичных чисел (Р 1од2а -logg.2), т.е. сумматоров , 3-1, , , соединены со входами элемента ИЛИ 5, выход которого вл етс выходом порогового логического элемента. Функционирование предлагаемого порогового логического элемента происходит следующим образом.The purpose of the invention is to increase speed and expand functional capabilities. 3 To achieve this goal, a threshold logic element containing K columns of adders, inputs of adders of the first column are connected to the input signal buses, an OR element is added, whose output is connected to the output signals bus, and inputs to the transfer outputs of adders (columns from P-gr to K-th, for threshold 2P, the outputs of each of the adders of the columns from the first to (Pl) are connected to the inputs of one of the sum of the tori of the subsequent columns, and the output of the sum of each of the adders of the remaining columns are connected to the inputs of one of the adders the transfer inputs of all columns are connected to the input signal buses.The drawing shows a threshold logic element for the case, the number of inputs equal to thirty-one and a threshold.The proposed threshold element for the case of the number of inputs equal to thirty-one consists of adders 1 -1-1-8, whose inputs are connected to the input buses of the threshold logic element, adders, 3-1, AND k of two-digit binary numbers, and the element OR 5, as well as inputs 6-36. The outputs of each two adders 1 are connected to the inputs of the corresponding adder 2, the transfer input of which is connected to the input of the threshold element. The outputs of the sum of adders 2-1 and 2-2 are connected to the inputs of the adder, and the outputs of the sum of adders 2-3 and 2-k - with the inputs of the adder 3-2. The inputs of the transfer of adders and connected to the inputs of the threshold logic element. The outputs of the sum of adders and are connected to the inputs of the last adder k, the transfer input of which is connected to the input of a threshold logic element. The transfer outputs of all adders of P-bit binary numbers (P 1od2a -logg.2), i.e. adders, 3-1,,, are connected to the inputs of the element OR 5, the output of which is the output of the threshold logic element. The operation of the proposed threshold logic element is as follows.

На выходах каждого из сумматоров 1 формируетс двоичный код числаAt the outputs of each of the adders 1, a binary code of the number is generated.

Claims

potential at the inputs 8-14 of the threshold element, a single potential appears at the transfer output of the adder 17 of the single potentials at their inputs. Binary codes from the outputs of each of the adders 1 are fed to the inputs of the corresponding adder 2, the outputs of which thus form the binary code of the number of unit potentials at the corresponding seven inputs. So, at the outputs of the adder 2-1, a binary code of the number m of unit potentials is formed at the inputs 8-14. Moreover, at the transfer output of adders 2-1, a single potential appears, if the number m of single potentials at the inputs 8-1 4 is greater or equal. At the outputs of the sum of the adder 2-1, the code of the number t m-Um / lj appears. Binary codes from the outputs of the sum of adders 2 are fed to the inputs of the corresponding adder 3, the outputs of which thus form the binary code of the number tf + t2 + tq, where t, i are the two-digit codes of the numbers that come to the inputs of this adder 3 s the outputs of the sum of the corresponding adders 2, and C 1. if the transfer potential of the adder 3, which is connected to the input of the threshold element, is fed to a single potential, and if this potential has zero potential. At the transfer output of adder 3, a single potential appears if t + t2 + t3 / 4. At outputs of transfer of adder 3; ob; t, + t2 + t3) - (t. + Code of number + t2 + t3 Binary codes from outputs of sum of adders, go to inputs of adder, at outputs of which binary code of number 2 binary codes of numbers received at the inputs of the adder C from the outputs of the sum of adders and, respectively, and if a single potential is applied to the transfer input of an h, if a zero potential is applied to this input. t + t2 + t37 / 4. Thus, whenever the number m of single units is at the inputs of the threshold logic element is greater than or equal to k, at the outputs of the transfer of adders of 2-bit binary numbers 2-1-2-4, 3-1, 3-2, k there is (t / 4) unit potentials. for example when feeding unit 2-1 units. If, for example, 3 unit potentials are applied to these inputs, then the transfer output of the adder 2-1 will have zero potential, and the output outputs of the sum will have unit potentials. .If the unit potential is also supplied to one of the inputs This causes a single potential at the transfer output of the adder. The appearance of a single potential at any of the transfer outputs of adders 2-1-2-3-J, 3-2, causes a single potential at the output of the element OR 3 with the inputs of which they are connected. Thus, whenever the number of unit potentials at the inputs of the threshold logic element is equal to or greater than the threshold a (in the case under consideration, a), a single potential appears at the output of the OR 5 element, which is the output of the threshold logic element. Consequently, the proposed threshold logic element has significantly greater functionality compared with (p prototype, since it implements any threshold function with a threshold of 1.2 ... .3) (n-1) of any number of variables. In addition, the proposed threshold the element has more speed than the prototype. For example, for a case, the prototype has a hold time T (18-8) of 1 :: 2, where Cz is the switching delay time of the total Matopa sum, depending on the order of connection of the adders in the adder units modulo two. In the proposed device, when i and the delay time is equal to ly i + 3Z +, rp, e g, the delay time of the two-bit memory matrix, Tj is the delay time of the OR element. In most cases, it is possible to accept. For example, for elements of the series 15, these values are not HC, HC. At the same time, Tr (3-5) is 2-3 times less, than in the prototype. Moreover, as the performance of the proposed device increases, it increases in speed with the use of the proposed device. The proposed device also provides a reduction in the equipment size 7. dovani It is achieved, firstly, by reducing the number of accumulators in its circuit, secondly, through the use of multi-digit adders, which is impossible in the prototype. For example, when the prototype contains 26 adders (one-digit), while the proposed device for a contains 22 adders (one-digit), i.e. 15% less. When implemented on a series 155 chip, the prototype requires 2b chips, and the proposed device 15, i.e. almost half as much. Thus, the proposed threshold logic element has significantly greater functionality, greater speed and a smaller amount of equipment. The invention The threshold logic element containing To the columns of the adders, the inputs of the adders of the first column are connected to the input buses, which means that, in order to improve speed, simplify and extend the functionality, the element OR is connected to the input bus signals, and inputs to the transfer outputs of the adders of the columns from the P-th to the K-th, for the 2P threshold, the outputs of each of the adders of the columns from the first to (P-1) -th are connected to the inputs of one of the adders of the subsequent columns c, and the outputs of the sum of each of the adders of the remaining columns are connected to the inputs of one of the adders of the subsequent columns, while the transfer inputs of the adders of all the columns are connected to the buses of the input signals. Sources of information taken in. attention during examination 1. USSR author's certificate No. 598252, cl. H 03 K 19/24, 1976.

2. USSR author's certificate number 683025, cl. H 03 K 19/23, 17.07.793. Author's certificate of the USSR in application V 2782136/21, cl. H 03 K 19/23, 25.12.79 (prototype).