SU1053104A1 - Multiplying device - Google Patents

Abstract

POSSIBLE DEVICE;.; containing an and-bit register multiplier (AND-bit resolution of decimal multipliers), (and -1) -bit register of the multiplicand with doubling scheme, summing unit, the output of which is the output of the device, is e so that, in order to increase speed, it contains the MaTjiHtsu from (and t () tt tetrad multiplication nodes, 2 AND tetrad summation nodes, 2 d buffer registers, 2 switchboards and 2 ti converting binary code to decimal, and the first inputs of the tetra multiply matrix nodes are connected to the outputs of the corresponding x tetrads of the multiplier register, and the second inputs — with the low-order outputs of the corresponding multiplier register, the inputs of the tetradic summation nodes are connected to (L outputs of the corresponding buffer registers and tetra multiplication nodes, and the outputs are connected to the inputs of the corresponding buffer registers and binary code to decade nodes as well as with the first inputs of the corresponding switches, the outputs of the binary: code decimal nodes are connected to the upstream inputs of the corresponding switches, you the moves of which are connected to the equilibrium inputs of the summation unit, the control inputs of the switches and the cytometer block, as well as the first control input of the multiplicable 1 register, are connected to the input of the device operation mode, the control inputs of the buffer registers and the multiplier register, and the second the control input of the register of the multiplicable is connected to the synchronization input of the device.

Description

The invention relates to computing and can be used in the development of high-speed devices for multiplying the numbers represented in the binary-decimal number system. A multiplying device is known that contains a drive (product shaping unit) and multiplied the multiplication factor. Henna factor 1 | u „.,. y, and the pre-cleaned multiplicative accumulator is added y, times, then it advances to the left one time and re-added to the accumulator y, once and so until all the bits of the multiplier ij are processed. The disadvantage of the device is low speed, especially when multiplying decimal numbers. Thus, to multiply two n-digit decimal numbers in a known device, time is required, roughly equal. see De tev, the time of summation of two and one-digit decimal numbers. Here it was assumed that the numbers O, 1, 2, ..., 9 appear in all categories of multipliers with equal probability. A single-ended multiplying device is known, containing n-bit multiplier and multiplier registers, a matrix of multiples and one-digit multipliers, and a set of one-digit adders for sug / 1g shirovaniya bit products. deny 2. Although the device has a high speed, it has the following significant drawbacks. First, on this device, not only with the multiplication of decimal numbers, perform the search and binary numbers, and therefore it cannot find wide application in modern general-purpose computers that use both a decimal and binary number system. second, the device requires a very large amount of equipment for its realization. The closest to the invention is a multiplying device that contains and is a 1m multiplier register and a decimal multiplier factor), and a 1 and 2 digit multiplier, a shift block, a summation block and a control block. The inputs of the control unit are connected to the outputs of the regressor multiplier, and the outputs are connected to the control inputs of the multiplicative and multiplier registers, as well as to the control inputs of the shift unit with the corresponding inputs of the summation unit, the output of which is device M. In the known device, the algorithm of decimal-binary multiplication of binary-decimal numbers 5j and; The multiplication time of two and-digit decimal numbers is approximately C, .v /, where t (4j is the sum of two 2ii-digit decimal numbers, ebifli time spent on the allocation of units / from the binary-decimal code multiplier, tq is the time of doubling (multiplying by two) multiplicand in the multiplicative register J 1,5 -and is a component that determines the average number of units in the binary decimal multiplier code. A well-known device can be used for unimportant changes. -; I is also called for multiplication of binary numbers; Sed. Therefore, we will further It is supposed that it allows multiplying besides decimal numbers and binary numbers. The main disadvantage of the known device is relatively slow speed. The purpose of the invention is to increase the speed of the multiplying device. -display bit register (n is the size of decimal multipliers r {-bit regotp multiplicand with doubling circuit, summing unit, the output of which is the output of the device, entered the matrix from (and t 0 1 knots for tetrad multiplication g 2 and tetrad sum nodes, 2p buffer registers, 2 AND switches and 2 h Nodes, converting the binary code to decimal, with the first; matrix inputs of the tetrad multiplication matrix connected to the outputs of the corresponding multiplicated register registers, and the second inputs - with the low-order outputs of the corresponding multiplier register tetrads, the inputs of the tetrad summation nodes are connected to the outputs of the corresponding buffer registers and tetrad multiplication nodes, and the outputs are connected to the inputs of the corresponding b Ferrous registers and converters of binary code to decimal, as well as with the first inputs of the respective switches, the outputs of the binary conversion nodes of the binary code are connected to the second inputs of the corresponding switches, the outputs of which are connected to the equilibrium inputs of the summation unit, the control inputs of the switches and the summation unit, and also, the first control is the input of the register of the multiplicand

connected to the input of the device operation mode, the control inputs of the buffer registers and the multiplier register, and the second control input of the register of the multiplicand is connected to the synchronization input of the device.

. Figure 1 shows the structural scheme of the proposed multiplier i device TTBaj in Figures 2 and 3 — possible embodiments of the tetradic summation node,. YU

The device contains FIG. q bit register 1 multiplier (and {size of decimal multipliers), n 4 1) -digit register 2 multiplicand with doubling circuit (doubling circuit 15 not shown, matrix 3 of (I4) n nodes 4 tetrad multiplication, 2 n nodes 5 tetradic summations, 2m buffer registers & 2, and 7 nodes. Binary code conversion to deads with 20, 2 switches 8, block 9 summation, input 10 of the device operation mode, input 11 of the synchronization and output 12 of the device. First inputs of the nodes 4 tetrad multiplication matrix 3 25

are connected to the outputs of the corresponding tetrads of register 2 of the multiplicand, and the second inputs are connected to the outputs of the lower bits of the corresponding tetrads of register 1 of the multiplier, the inputs of nodes 5, "tetrad summing are connected - to the outputs of the corresponding buffer registers b and nodes 4 tetrad multiplication, and the outputs are connected to the inputs of the corresponding buffer registers 6 and the nodes 7 for converting the binary code to the decimal 5, as well as with the first inputs of the corresponding switches 8, the outputs of the KNOTS 7 for converting the binary code into the decimal 7 connect Us with the second inputs of the respective 40 switches 8, the outputs of which are connected to the equilibrium inputs of block AE; -9 summation, control the inputs of the switches 8 and the summation block 9, as well as the first control input of the multiplex register 2 of the device; The control inputs of the buffer registers b and register 1 of the multiplier, as well as the second control input of the register 2 50 1 ″, are connected to the input 11 of the synchronization time of the device.

The input 10 of the operation mode is intended for setting the device to multiply binary or decimal villages. So, for example, if high potential is present;

the device performs the multiplication of binary numbers, S otherwise it is tuned to the multiplication of the decimal numbers. Device input 11 is synchronized. The signal at this input simultaneously shifts the information by one bit in the tetrads of the register 1 of the multiplier towards their younger 65

bits, doubling the contents of the register of 2 multiplicand and receiving information in the buffer registers 6 of the device. The register.1 multiplier can be built on two-stroke synchronized D-triggers. It should provide for a circuit of information shifting by one binary bit in the direction towards the low order bits either in all binary bits or only in binary bits of tetrads. Register 2 multiplicand - (ni--) - bit. The extra () th (tetrad) bit is introduced to eliminate the distortion of information in register 2 of the multiplicative after performing multiple military events in it (the contents of register 2 of the multiplicable in the multiplication process are doubled three times, i.e. as a result, it is multiplied by eight ). This register, as well as register 1 multiplier, can be implemented on push-pull synchronous D-triggers. The duplication circuit in register 2 can be designed as in a known device. In nodes 4 of a tetrad multiplication matrix 3, the product of the contents of the corresponding tetrad of register 2 is multiplied by the low-order value of the corresponding

.trands register 1 multiplier. Each: node 4 can be implemented on four two-input elements I.

All nodes 5 "tetradum sums are of the combined type. In each operation cycle of the device in these nodes, the tetradic works are generated 1m generated in a given cycle at the outputs of the corresponding 4 multiplexed nodes and added to the resultant content of the corresponding buffer register 6 formed on the previous device operation cycle. Since in sys- tems 5 of tetrad sugralization, located in different weight positions, sushi / different number of tetrad works are measured, their circuit structures will differ somewhat (this is true for buffer registers 6, nodes 7 for converting binary code into decimal and commutator eight) . Therefore, we consider in detail the schematic structures of the nodes located only in the second weight position (the first weight position has the lowest weight). Consideration of the circuit structure of node 5 tetrad summation will be carried out together with the analysis of the circuit structure of the buffer register 6. Initially, we estimate the minimum size of the buffer register b. It must be determined provided that the device processes binary operands, since when multiplying decimal numbers, the buffer register size may be less. In the upper node 7 of the tetrad notebook, located at the second weight position, the following maximum possible values of the tetrad works 1–111, 1111, and 1111 (the sum of these products is equal to 101101) are formed during the first device working hours, while in this node 4, the products nil, 1110 and 1100 are formed (their sum is equal to 101001). The tetra products, which are formed with in the last (fourth) operation cycle of the device, are not taken into account here, since this step does not record information in the buffer register 6. So, at the output of node 5 of the tetrad one, the result is summed up in the third cycle of operation of the device; Similarly, it can be shown that when multiplying decimal numbers, it suffices to use the sixth regular buffer register b. Taking into account THAT in FIG. 2, a functional diagram of the tetrad-summing node 5 together with the buffer register b scheme is included, which includes seven two-stroke synchronous D-triggers 15. The tetrad-summing node 5 contains four one-digit binary adders 13 and six-bit binary combinational adder 14 with the accelerated formation of bit transitions. noses. The tires 16 and 17 enter the works of the tetrad addition node 5, formed at the outputs of the upper and lower nodes 4 tetrad multiplication, respectively. In each operation cycle of the device in the node 5 of the tetrad summation, the summation of three components is made: the first tetradic product arriving along the tires 16-; . the second tetrad work supplied by tires 17; the contents of the buffer register 6. The result obtained in the node 5 is written to the buffer register b with the resolution of the signal at the synchronization input 11 of the device (in the last fourth device operation cycle, the information is written to the buffer register is not made). An embodiment of node 5 (FIG. 3 allows for a faster device for multiplying numbers. According to this variant, node 5 tetra. Summation contains a cascade 18 of one-bit binary adders 13, the output of which sum is 1/2 tetrad works is formed in a two-row code / bit sums are written to the top of the scientific research institute of triggers 15 of register 6, and the bit transfers are written to the lower number of triggers 15). The higher performance of the node 5 of the tetradic summation is ensured by the fact that in the first three cycles of operation of the device it does not bring the two-way code into the one-way one (which, as a rule, requires considerable time), and only One code is reduced to a single code on the combinational adder 19 with the accelerated formation of bit transfers. Similarly, other circuit structures of the tetrad sum nodes 5 can be developed. The results displayed at the outputs of the binary-to-decimal conversion nodes 7 are used in the device only in decimal multiplication. These nodes are designed to "reclaim the binary code generated at the output of the corresponding node 5 of the tetrad summation in the last operation cycle of the device." Into a binary-decimal code (for example, into code 8421). They can be built using high-speed ROMs on truth tables by known methods. For definiteness, consider in detail the synthesis of the node 7, located at the second weight position of the device. First, it is necessary to determine /, which maximum value of a binary code should transform this node. In this case, we will be guided by the following. In the upper node 4 tetradic multiplication, located at the second weight position, the following maximum possible values of tetrad works, 0000, 1001, 1001 and 1001, can be formed during the four cycles of the device when multiplying the decimal numbers time, as in the lower node 4, only such possible maximum works can be formed: 0000 ,, 1001, 1000 and IT (the maximum values of the tetrad works are possible in the device only when two 1 digits of digits is equal to nine - code 1001), and the two lower digits of the multiplier are seven - (code Olllj. Therefore, at the output of node 5 of the tetrad summation located in the second weight position, after executing four clock cycles, a binary code value exceeding the value of 110010, since 1001 + 1001 + 1.001 + 1001 + 1000 + 0110 (116010) 2 (50), (o, a. Therefore, the binary conversion to decimal section 7 can be built on ROM with a capacity of fifty one seven-bit binary word So, for example, if you send a ROM to the address input

binary code 001111, at its output a binary-decimal code 011.0101, which is numerically equal to the decimal code, must be formed — the incoming to the address input ROM. Node 7, located at the second weight position, however, like the other nodes 7 of the device, can be implemented on the basis of

widely used integrated circuits of the K155 series, in this series there is a special element PR7 converting a DI OOID code to a decimal 7j. The switches 8 in the binary U1 multiplication mode connect to the inputs of the summation unit 9 — the outputs of the tetrad drying units 5 and in the ten mode of multiplying the outputs of the binary conversion units to the binary one.

Thus, in the proposed device, nodes 5 and 7, as well as buffer registers 6 and switches 8, located at different weight positions, will also have different circuit structures. If it is necessary to ensure uniformity of the structure of the device, it is possible to limit only the detailed analysis and synthesis of nodes 5 and 7, the buffer register 6 and the switch 8 located on the I-th weight position, and this combination can be constructively implemented as a single module used at all weight positions. x devices and implemented, for example, as a large integrated circuit (in Fig. 1, this module is marked with dashed lines).

Block 9 is designed to summarize the results

Formed at the outputs of the tetrad-summing nodes 5 (in the mode; binary multiplying or converting binary code 7 nodes into the decimal (in the decimal clever mode), after performing four tat of device operation. It is assumed that this block is of the combinational type. The output, which is also the output 12 of the device, forms a 2c-bit product when multiplying decimal numbers and an 8ts-bit product when multiplying binary numbers. The schematic structure of the summation block 9 depends on the size of the multiplied numbers El.Tak when multiplying two-digit decimal and eight-bit binary numbers as a block of 9 summation

 A fast two-input combinational adder can be used to add binary and decimal numbers 3. . When multiplying larger digits, it may be necessary to use a three-input adder or an adder with an even greater number of inputs. In most cases, the device

As a summation unit 9, a two-input or three-input high-speed parallel combination adder is used, which allows to add both binary and decimal numbers (a three-input adder can be built on the basis of two two-input adders connected in series).

The multiplying device operates as follows.

For definiteness, consider the mode of decimal multiplication. In the initial state, in register 1 the multiplier holds the C-bit multiplier, in register 2 of the multiplicator the P-discharge multiplier, the buffer registers 6 are zero (the signs of the multipliers are not considered, and it is assumed that the multipliers are in the direct code) . At the input 10 of the operating mode of the device there is a low potential, which means g {II, that the device is set to multiply decimal numbers. In this case, in the register 2 of the multiplicable circuit, the doubling of its contents is included, the outputs of the binary conversion to decimal nodes 7 are connected via switches 8 to the corresponding inputs of the summation unit 9, which, in turn, is configured to add decimal numbers,

In the first cycle of operation of the device, tetrad works are formed in the nodes 4 of the matrix 3, which are further summarized taking into account the weight positions they occupy in the corresponding nodes 5 of the tetrad summation. The first 5th clock cycle of the device ends with the arrival of the first clock pulse at the input 11 of the device, which simultaneously records the results from the outputs of nodes 5 into the corresponding buffer registers, shifting information by one bit in the direction of the lower bits in the tetrad of the 1 multiplier and doubling the contents register 2 multiplicand. :

In the second and third cycles, the device works in the same way.

The main difference in the operation of the device in the fourth final cycle is that the clock pulse does not arrive at the device input 11, and the results generated at the output of nodes 5 of the Tetrad summation, after their preliminary conversion at nodes 7, through the switches 8 arrive at the corresponding inputs of the summation unit, at the output of which the final 2g1-bit product is formed.

So, regardless of the size, numbers multiplied, the final result is formed by; four clock cycles, and the multiplication time of two o-decimal numbers is approximately equal to Tl -i4 + -5 2V4 -l-5 tj + tg iq, where tp is the information delay- at the node with the sequence number P- (it is assumed that t and ti 4, -2, which is quite realistic). When multiplying binary numbers, the main difference in the operation of the device is that in register 2, the doubling of its contents actually reduces to a simple shift of information in it by one binary digit to the left, the summation unit 9 doesn’t count on the summation of binary numbers and in the latter ( the fourth) operation cycle of the device, the results, formed at the outputs of nodes 5 tetradic summation, mines 7 converting binary code to decimal, are transmitted through co-switches 8 to the corresponding inputs of block 9 sum world . The multiplication time of four bits of binary numbers is a value. 3- (In the known device, the multiplication time of two .C-discharge decimal numbers is approximately equal to TS. While it is in the proposed device, the value is TS 3-i-t4 5 2Ut.4 + lg + t7Vt8 + -tg. Let 11 8, t € 14 ,, tuA8 6 (J, 4,, i2 tt | ABx 6-, 7 8- And i9 2tcM 281), where the delay is on one logical element. Then, at that time, as t 79, i.e., the proposed device has approximately 3.5 times higher performance than the known one. The multiplication of binary numbers in a known device takes place over time (well.,. 1, and in the proposed device this time is approximately equal to Tf 3 (,) H4H5Hg4i. Then taking into account accepted assumptions, we obtain that v.TjV.TtJ :, and, therefore, multiplication of binary numbers in the proposed device is performed approximately 5.2 times faster than in the well-known one. Thus, the technical and economic advantage of the proposed multiplying device in comparison with The known one is much faster, for example, the multiplication of eight-digit decimal numbers is performed in it about 3.5 times faster than in the known device. By multiplying the same binary numbers, there is an even greater gain in speed. Thus, multiplication of 52-bit Binary numbers is about 5.2 times faster. However, such a significant increase in the speed of the device is achieved with moderate expenditures of the equipment used in it, since the multiplication of decimal numbers is performed mainly on the same equipment as the binary numbers.

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Claims (2)

MULTIPLE DEVICE,.: Containing the and -bit register of the multiplier (AND is the bit of decimal factors), (and b <) is the bit register of the multiplier with the doubling circuit, the summing unit, the output of which is the output of the device, distinguishes it that, in order to improve performance, it contains a matrix of (and t <) η nodes of tetrad multiplication, 2 And the nodes of the tetrad summation, 2 and buffer registers, 2 And the switches and 2h nodes of converting the binary code to decimal, the first inputs of the nodes of the notebook multiplication of the matrix are connected to the outputs of the corresponding notebooks of the register of the multiplier, and the second inputs - with the outputs of the younger bits of the corresponding notebooks of the multiplier, the inputs of the nodes of notebook copying are connected to the outputs of the corresponding buffer registers and nodes of the notebook multiplication, and the outputs are connected to the inputs of the corresponding buffer registers and nodes of the conversion When binary code is decimal, as well as with the first inputs of the corresponding switches, the outputs of the binary to decimal conversion nodes are connected to the second inputs of the corresponding switches, the outputs of which are connected to the equilibrium inputs of the summing block; the control inputs of the switches and the summing unit, as well as the first control input of the multiplier register are connected to the input of the device operation mode, the control inputs of the buffer registers and the multiplier register, as well as the second control input of the multiplier register are connected to the synchronization input of the device. „SU ... 1053104