SU1126946A1 - Translator from binary-codeded k-ary code to binary code - Google Patents

Abstract

CONVERTER dyadic kIChNOGO code into a binary code comprising a group of bit counters, pulse generator, a group of AND gates, flip-flops group condition, the equivalent generator, and to accumulate telyshy adder vsody which are outputs of the converter and the inputs connected to respective output of the equivalent the first group of inputs of which are connected to the outputs of the corresponding group state triggers and with the first inputs of the corresponding elements AND of the group, the outputs of which are connected to the counting inputs mi-counters of the corresponding bits, in addition to the group's lower-order counter, are different and in order to improve speed, a group of zero decoders is entered into it, and the equivalent driver contains a decoder and an encoder, the first group of inputs of which is connected to the corresponding outputs decoder, and the second group of inputs of the encoder is connected to the second group of inputs of the imager equivalent and with the corresponding outputs of the low-order counter of the group, the bit outputs of all of the bit counters, except for the the low-order bit of the group is connected to the inputs of the zero-decoder groups, the outputs of which are connected to the synchronous inputs of the corresponding group state tripers, the B-inputs of which are connected to the direct output of the pulse generator, the direct delayed output of which is connected to the synchronous input of the accumulative adder and the inverse output of the generator and mycoc is connected to the second inputs of the elements AND of the group, O) O) the formation inputs of the discharge counters of the group are the inputs of the converter, the outputs of the encoders are the outputs of the the equivalent cell and the inputs of the decoder are the first group of inputs of the equivalent cell.

Description

1 The invention relates to computing technology, namely to information conversion devices, and can be used in specialized digital systems for measuring and transmitting information. The converter is known to be a binary, 1 -ich code, based on a parallel counting binary binary -character counter for addition, containing groups of binary bits of a binary double-K-ary counter, a comparison circuit, and a pulse generator G. The disadvantages of the known device are low speed (the conversion time depends on the value of the code being converted and can be maximally equal to two cycles and the lack of possibility of introducing corrections in the code. The closest to the proposed one is a converter of a non-position code into a binary code containing a bit group one of the counters, a pulse generator, a group of elements I, a group of triggers of state j, a group of elements I, a forwarder of equivalents and a cumulative adder, whose inputs are connected from the output and a driver of equivalents, the inputs of which are connected to the outputs of the group state trigger, and the OUTPUTS of the elements AND group are connected to the counting inputs of the bit counters in group 1.21. The disadvantage of this converter is relatively low speed, the action associated with the sequential method the conversion of the individual K-ary bits,. The purpose of the invention is to increase the net conversion of the converter into the set goal. Thus, in the converter of the binary code into the binary code containing the group of bit counts. ov, a pulse generator, a group of elements B-I, a group of state triggers, form €; only € €; nta and accumulator adder J outputs. Which are the outputs of the converter, and the inputs are connected to the corresponding outputs of the former equivalent, the first group inputs are connected to the outputs of the corresponding group state triggers and with the first inputs of the corresponding elements AND groups whose outputs 62 are connected to the counting inputs of the counters of the corresponding bits, in addition to the counter of the lowest bit of the group, are entered a group of decoders zero 5 and a driver equivalent to a decoder and an encoder, the first group of inputs of which is connected to the corresponding outputs of the decoder, and the second group of inputs of the encoder is connected to the second group of inputs of the equivalent generator and the corresponding outputs of the low-order counter of the group, the outputs of all bits The counters, except the low-order counter of the group, are connected to the inputs of the zero-group decoders, the outputs of which are connected to the sync jacks of the corresponding triggers of state g groups 5 The inputs of which are connected to the DIRECT, pulse generator, the rest of my delayed is connected to: the synchronous input of the cumulative adder, and the inverse output of the pulse generator is connected to the second inputs of the elements AND groups, the information inputs of the discharge of the group counters are inputs of the converter, the outputs of the encoder are the outputs of the shaper of the equivalent, and the inputs of the decoder are the first group of inputs of the shaper of the equivalent. On the drawing there is a block diagram of the proposed device, gp 3, where n is the number of K - EXEMPTION bit - don. The converter of the binary-K-ary code into the binary code is sodernsn: g group of counters 1, generator 2 pulses containing right my P,. direct delayed PZ and inverse; And outputs, a group of triggers 3. (current .go). State, shaper 4 equivalent .; combinational binary adder 5 and register 6 of the result, a group of elements And 7 and a group of dennfrators of zero 8.. In the proposed device, formiropate 4 equivalents are made j in the form of a series-connection; x x encoder 9 and encoder 10 and in particular case implements the function: S 2 Citl44-C ,, 4r728 3 С., С Where С J С, -5 С - The values of the binary status code, the combinium, and the totalizer 5 and 6 of the result together form the cumulative adder P. The control, initiation and reset circuits are not shown in the drawing. Since, the range of the input code O is changed (12-1). The state code of a binary-12-second counter has values from 000 to 1, each of p-3. The digits of which correspond to the presence (1) or absence of I O) of information in each of the three senior groups of bits of double-12 counter. Formate 4 converts. the binary code of the state (in) in the binary term, according to the following table (next to the bit of the binary code on the right). Translating 4 binary times of the lower group of bits of a binary 12 code The device works the next time. Let it be required to convert the input binary-12-ary code of the numbers 0010 OOP 1000 9 1728 + 2-14 +3 12 8 15552 288 36 + 8 15B84. In the initial state, the result register 6 is reset, on the direct output of generator 2 - low level; 6D at the inverted output of the generator 2, at the inverted outputs of the triggers 3 group states and outputs of the And 7 group elements - a high level. Writing the unit of account to the counter 1f addition to cy mate 5, as well as recording information into the 3 triggers cocTO.ftININ group is performed by a 0 differential, the indication of transfers in the counter 1 and the recording of information in the result register 6 is performed by a differential. With the arrival of the leading edge of the first positive impulse c. the direct output of the generator 2, the state code of the triggers 3 does not change. At the outputs of the elements And 7 and the read-out inputs of the counter 1 is low. The status code 11 1 enters the E :: Oda driver 5 and converts to the binary code of the number 1884. Access from the direct delayed output of the generator 2, the leading edge of the first positive impulse resolves the addition of the numbers O and 1884, and the faddy front of the same impulse will overwrite the information from the outputs of the adder 5 into the register 6 of the result, setting the binary sum of the number 1884 on the second summing inputs of the sum 5; With the arrival of the trailing edge of the first negative pulse from the inverse output of the generator 2 along the positive P8repad5 at the output The number of elements U 7 in the counter .1 is set to the number ci lOOOOOOl 00.10 1000 14000, i.e. The contents of the str (the first groups of bits of counter 1 are simultaneously decremented by one. With the second pulse, the state code does not change. The output of the formers 4 is the binary code of the number 1884, the leading edge of the second delayed positive pulse will allow the addition of numbers 1884 and 1884, and the rear the front of the same pulse will overwrite the result of the summation into the register 6 of the result, setting the binary value of the number 3768 to the second cyrc ty inputs of the adder 5 and the back edge of the second negative pulse will set the number 0000 00 in the counter. 01 1000 121: 6 With the arrival of the leading edge of the third negative pulse, the positive 1-pulse of transfer from the output of groups of bits 1 of counter 1 changes the status code to 101, (stepwise at the outputs of the generator 4

- s

the binary code of the number 1740, the leading edge of the third delayed positive pulse will allow the addition of the numbers 3768 and 1740, and the falling edge of the same, the pulse will set the second summing inputs of the adder 5 to the binary value of the number 5508, the falling edge of the third negative pulse passes the subtracting inputs of the groups: Iv and 14 counts I in accordance with the status code and sets the number to 1.

 0000 0000 1000 10376

With the arrival of the next six pulses in accordance with the state code 100 in Summathara 5, the successive summation of the terms 1728 in the binary code is performed, and in the older group 1 of the counter 1, the consecutive subtraction of six pulses.

In the same way OQOQ.OOOO

In register 6 of the result, after 9 pulses (the conversion cycles, the binary code of the number 15876 is set. With the arrival of the leading edge of the tenth negative pulse, the state code 000 is set. In this case, the 4 equivalent generator translates the bit binary code of the younger group of the counter 1 to the corresponding four first The summing inputs of the adder 5. The leading edge of the tenth delayed positive pulse will allow the addition of numbers 15876 and 8, and the falling edge 3 of the same pulse sets the binary code of the number 15884 you odes device. In this conversion process terminates

Before each subsequent conversion, the result register 6 and the counter j must be zeroed.

466,

The presence of a binary-12-bit reversible counter provides the ability to work in the counting mode and introduce corrections in the unitary code

In the proposed device, it is possible to directly introduce an amendment in binary code. To do this, it is enough to connect the HJBi elements, the number of which corresponds to the width of the correction code by the first inputs to the outputs of the imager 4 equivalents, and the outputs to the first information inputs of the adder 5, The second inputs

the OR elements are the inputs of the corresponding bits of the binary correction code. In accordance with the sign of the amendment code, the sign mode of the adder 5 and in the register 6 of the result on the trailing edge of the CMP: lsa

entering the correction is fixed by cyMi-ia. or the difference of the converted number and the correction.

The performance of the proposed device does not depend on the width of the code being converted and is not determined. Next, the conversion cycles (3 of our case 12, while the time of the prototype conversion depends on the size of the code being converted). So, for oio 15884 i001 OOP 1000, the conversion time in the proposed device is 10 t., And in the prototype 22 cycles.

The proposed device is faster than the known devices of sequential conversion (including machine ones) and is second only to the devices of direct conversion, being simpler than the latter in hardware and algorithmic implementation,

Claims (1)

Binary-to-binary code converter to binary code, containing a group of bit counters, a pulse generator, a group of AND elements, a group of state triggers, an equivalent driver and a storage adder, the outputs of which are converter outputs, and the inputs are connected to the corresponding outputs of the equivalent generator, the first group of inputs of which is connected to the outputs of the corresponding triggers of the group state and to the first inputs of the corresponding elements AND groups, the outputs of which are connected to the counting inputs of the count sensors of the corresponding digits, except for the counter of the lowest digit of the group, which is characterized by the fact that in order to improve performance, a group of zero decoders is introduced into it, and the equivalent driver contains a decoder and encoder, the first group of inputs of which is connected to the corresponding outputs of the decoder and the second group of inputs of the encoder is connected to the second group of inputs of the equivalent driver and to the corresponding outputs of the counter of the least significant bit of the group, the bit outputs of all bit counters, except the counter under of the first discharge of the group, connected to the inputs of the zero decoders of the group, the outputs of which are connected to the sync inputs of the corresponding triggers of the group state, the B-inputs of which are connected to the direct output of the pulse generator, the direct delayed output of which is connected to the synchronous input of the accumulative adder, and the inverse output of the pulse generator connected to the second inputs of the AND elements of the group, the information inputs of the bit counters of the group are the inputs of the converter, the outputs of the encoders are the outputs of the equivalent driver, and in decoder moves are the first group of equivalent driver inputs. SU, ... 1126946> ί 112