SU1152044A2 - Storage with self-check - Google Patents

Abstract

1. A STORAGE DEVICE WITH SELF-MONITORING by author. St. No. 748515, characterized in that, in order to improve speed and increase the effective capacity of the device, an element is entered into it, the output of which is connected to one of the inputs of the control unit, and the inputs are connected to the outputs of the control unit, one of the inputs of the third number register is connected to exit peraqro register numbers. 2. The device according to claim 1, characterized in that the control unit contains Triggers one through four, a group of elements AND one through six, elements OR one through four, and delay elements one through six, the unit output of the trigger being connected to the first inputs of the first and second elements And groups, the second inputs of which are connected respectively to the unit and zero outputs of the second trigger, the output of the first element And group is connected to the first. the input of the second element SHS, the output of which is connected to the input of the second delay element, one of the outputs of which is connected to the first input of the first OR element, the output of which is connected to the zero input of the first trigger, the output of the second AND element of the group is connected to the input of the first delay element, one of the outputs which is connected to the second input of the second OR element, and another output to the single input of the second trigger and the second input of the first OR element, another output of the second delay element is connected to the first inputs of the third and of the fourth AND group, the second inputs of which are connected respectively to the single and zero outputs of the third trigger, the outputs of the third and fourth elements of the AND group (L are connected respectively to the inputs of the fourth and third delay elements, one of the outputs of which are connected to the inputs of the third OR element, whose output connected to the zero input of the third trigger; another output of the fourth element, the holder's jam, is connected to the first inputs of the fifth and sixth elements AND groups, the second inputs of which are connected To the unit and zero 4 4 outputs of the fourth trigger, the outputs of the fifth and sixth elements AND groups are connected respectively to the inputs of the sixth and fifth delay elements, one of the outputs of which are connected to the inputs of the fourth OR element, the output of which is connected to the zero input of the fourth trigger, the other output of the sixth delay element is connected to the zero input of the second trigger, the single inputs of the first, third, and fourth triggers are one of the inputs of the control unit.

Description

IM The invention relates to computing. According to the main auth. (748515, there is a device containing the first group of elements OR, the first address register, the address counter, the battery, the outputs of which connect the first inputs of the first, second and third terms of its number registers and one of the inputs of the fourth number register, the second a group of OR elements, a control unit, the first and second switches, a bit counter, a control unit and a monthly control unit, the accumulator outputs connected to the outputs of the first group of OR elements, whose inputs are connected to the outputs of the first and second registers ad the second register of the address register is connected to the output of the address counter, the output of the first register of the number and the first output of the second register of the number are connected to one of the inputs of the second group of OR elements whose output is connected to the output of the accumulator; with the output of the local control unit and the first we enter the control unit, the second input of which is connected to the output of the third register of the number, another input of the fourth register of the number to the output of the first switch, and the outputs of the fourth register The second and third inputs of the first and second switches correspond respectively to the first outputs of the control unit and the bit counter, the second output of the control unit is connected to the other inputs of the second group of OR elements and the first input of the second switch, the output of which is connected to the first input of the first switch. to the output of the bit counter, the second output of which is connected to the input of the control unit, one of the outputs of the control unit is connected to the equalizing inputs of the accumulator, the first and second address registers, the address counter, the first, torogo, third and fourth p giste number control unit and the local control unit, the other outputs of the control unit are connected with the control inputs of the first and second switches. In the device, the failed bits of the working cells are replaced by the bits of the backup cells jj. 4 The disadvantages of the known device are low speed and low effective capacity, since the substitution of the failed bits of the working cells is carried out even if the type of failure is matched with the recordable symbol. The purpose of the invention is to increase the speed and increase the effective storage capacity. The goal is achieved by introducing an AND element into the memory with self-control, the output of which is connected to one of the inputs of the control unit, and the inputs are connected to the outputs of the control unit, with one of the inputs of the third number register connected to the output of the first number register. In this case, the control unit contains the first to the fourth triggers, the first to the sixth group of elements, the first to the fourth IL elements, and the first to the sixth delay elements, the unit output of the first trigger is connected to the first inputs of the first and second elements of the And group, the second the inputs of which are connected respectively to the unit and zero outputs of the second trigger, the output of the first AND element of the group to the first input of the second OR element, the output of which is connected to the input of the second delay element, one of the outputs of which is n It is connected to the first input of the first OR element, the output of which is connected to the zero input of the first trigger, the output of the second element AND of the group is connected to the input of the first delay element, one of the outputs of which is connected to the second input of the second element. / or the other output to the single input the second trigger and to the second input of the first element OR, the other output of the second delay element is connected to the first inputs of the third and fourth elements of the AND group, the second inputs of which are connected respectively to the single and zero inputs third the first trigger, the outputs of the third and fourth elements of the AND group are connected respectively to the inputs of the fourth and third delay elements, one of the outputs of which are connected to the inputs of the third element OR, B1, whose input is connected to the zero input of the third trigger, the other output of the delaytochch delay element - to the first inputs of the fifth and sixth elements AND groups, the second inputs of which are connected respectively to the unit and zero outputs of the fourth trigger, the outputs of the fifth and sixth elements And group, respectively, to the inputs of the sixth and five delay elements, one of the outputs of which are connected to the inputs of the fourth OR element, whose output is connected to the zero input of the fourth trigger, another output of the sixth delay element to the zero input of the second trigger, the single inputs of the first, third and fourth triggers are one from the inputs of the control unit. FIG. 1 shows a block diagram of a self-monitoring memory device; in fig. 2 is a block diagram of a control unit (e.g., for a recording mode); in fig. 3 - one of the possible options for the control unit. The device (Fig. 1) contains a drive 1 having inputs 2, the first group of elements OR 3, the first 4 and the second 5 address registers. Register 4 has inputs 6. The device also contains a 7-address counter. One of the inputs of the first register of the 9th number is connected to the outputs 8 of the accumulator 1. The device also contains the second 10, third 11 and fourth 12 registers of numbers, the second group of elements OR 13, the control unit 14, the first 15 and the second 16 switches, the counter of 17 bits, the control unit 18, the local control unit 19, the element And 20. The device has an input 21 and an output 22. The element AND 20 have e-inputs 23 and an output 24. The control unit 18 (FIG. 2) contains the first to fourth triggers 25-28, and the elements 29-34 from the first to sixth, elements OR 35-38 first to fourth, and elements 39-44 of delay from first to sixth. The control unit 14 (FIG. 3) contains the shift register 45, the register 46, the elements OR 47, and the AND 48 elements. The device operates as follows. In the initial state, the counter 47 is reset. For each linear section of the program or for an array of numbers that will be recorded sequentially, backup cells of drive 1 are allocated. Counter 7 records the address of the first backup cell, and input 6 of register 4 receives the address of the first cell of the array to be written or read. numbers When writing, the number through input 21 goes to register 9, and through the elements of OR 3 the contents of register 4 are fed to the input of drive 1. The direct code of the number from register 9 is entered into the resistor 11 and through the elements of OR 13 is written into the cell of drive 1. Then reading the direct code from accumulator 1 to register 10. The contents of registers 10 and 11 are fed to block 14. If there are no failed bits in the cell or the type of failure is the same as the characters to be written, then the next address is supplied to register 6 input and the same is done wto ry number. If the contents of registers 10 and 11 match, the outputs of control unit 14 will be all single signals, which, through element 20, arrive at control unit 18, which generates control signals for recording the second number. If in the cell there are failed bits and the type of failure does not match the value of the written symbol, then the corresponding bits of registers 10 and 11 in block 14 of the control do not match, and the inputs of the And 20 element will have the corresponding number of zero signals. On the zero signal element And 20 block 18 organizes the operation of the device in the following sequence. Record the return code from register 9 through the elements of the ШШ 13 into the cell of accumulator 1, and the contents of the cell are read into register 11. After this, the direct code of the number is written to register 10. The contents of registers 10 and 11 are fed to block 14. The last and the counter 17 assigns on each switch 15 the signals for which from register 9 the lower bits of register 12 are transferred to the digits of the number, corresponding to the failed bits of the cell. Then, from block 14, a code corresponding to the number of failed cell bits is written to the counter 17 bits. From block 18 to block 19, a signal is received by which the marker 1 of cell S1 of power 1 through register 10 is written to code 1. Similarly, the number is written to the second failed cell, in which the type of failed bits is not consistent with the recording of the tuat symbol, only the corresponding register bits 9 are written to the next lower empty bits of register 12. After all bits of register 12 are filled, the counter 17 bits generates a fill signal in block 18. The address of the cell's reservist from counter 7 goes to register 5 and through the ground nty OR 3 at input 2 of accumulator 7. The contents of register 12 through the elements OR 13 are written into the first backup of the array of numbers. After that, the signal from block 18 to the midpoint (the eater 7 generates the address of the next backup cell. The information is read next.) In register 4, the address of the first cell of the read array Jsc is given, and the address of the first reserve cell of the array of numbers is written into counter 7. The counter 17 is in the zero state.The signal from block 18 transmits the contents of counter 7 through register 5 and the elements OR 3 to input 2 of drive 1. A read is made from the first backup cell to register 12. Then, from register 4, a The address of the first cell of the 46th array of numbers is read to registers 9 and 10. If the marker code is O, then, therefore, the cell has no failed bits, and the number from register 9 goes to output 22. If marker code 1, then the read-back code of the number is written to register 11. The contents of registers 10 and 11 are fed to block 14. Signals from block 14 and counter 17 send the lower bits of register 12 to register 9 via the switch 16. The J spikes of the failed cell are thus replaced by the discharge Reserve cells. The number from register 9 nocTjmaeT is output 21. Counter 17 records the code corresponding to the number of register bits 12 used. If all the bits of register 12 are used, as indicated by the corresponding state of counter 17, then by a signal from block 18 the address of the next backup cell is generated in counter 7. The contents of the backup cell are read into register 12, and the array of numbers continues to be read in a similar way, replacing the failed bits. The proposed device requires fewer numbers than the known reserve cells and is more fast. 19 UIJ

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Claims (2)

1. MEMORY DEVICE WITH SELF-CONTROL by ed. St. No. 748515, characterized in that, in order to improve performance and increase the effective capacity of the device, an element And, the output of which is connected to one of the inputs of the control unit, is inserted into it, and the inputs are connected to the outputs of the control unit, and one of the inputs of the third register of the number is connected to the output of the first register of a number. 2. The device pop. 1, characterized in that the control unit comprises first to fourth triggers, a group of AND elements from first to sixth, OR elements from first to fourth and delay elements from first to sixth, wherein the single output of the trigger trigger is connected to the first inputs of the first and second elements And the groups whose second inputs are connected respectively to the unit and zero outputs of the second trigger, the output of the first AND group element is connected to the first. the input of the second OR element, the output of which is connected to the input of the second delay element, one of the outputs of which is connected to the first input of the first OR element, the output of which is connected to the zero input of the first trigger, the output of the second AND element is connected to the input of the first delay element, one of the outputs which is connected to the second input of the second OR element, and another output to the single input of the second trigger and the second input of the first OR element, the other output of the second delay element is connected to the first inputs of the third and four of the first AND element group, the second inputs of which are connected respectively to the single and zero outputs of the third trigger, the outputs of the third and fourth elements of the And group are connected respectively to the inputs of the fourth and third delay elements, one of the outputs of which are connected to the inputs of the third OR element, the output of which is connected to the zero input of the third trigger, the other output of the fourth delay element is connected to the first inputs of the fifth and sixth elements AND groups, the second inputs of which are connected respectively to a single the fourth outputs of the fourth trigger, the outputs of the fifth and sixth elements AND groups are connected respectively to the inputs of the sixth and fifth delay elements, one of the outputs of which are connected to the inputs of the fourth OR element, the output of which is connected to the zero input of the fourth trigger, the other output of the sixth delay element is connected to zero the input of the second trigger, the single inputs of the first, third and fourth triggers are one of the inputs of the control unit. SU „. 1152044 1 1152044