SU1129727A1 - Device for selecting pulse signals - Google Patents

Abstract

A DEVICE FOR SELECTING PULSE SIGNALS, containing a reversible pulse counter, the summation and subtraction inputs of which are connected to the outputs of the first and second elements, respectively, and the bits of the outputs to the inputs of the reference code decoder, the second group of inputs of which are connected to the outputs master code, the inverter, the output of which is connected to the first input of the second element And, the input to the input bus and the first input of the first element And, the second input of which is connected to the first output pulse generator, the third element And, the output of which is connected to the input of the installation of the reverse pulse counter in the zero state, RS-flip-flop, the output of which is connected to the output bus, characterized in that, with the noise immunity enhancement circuit, a quarter element is introduced into it, whose entrance is connected to; .the output of the reference element, the second input with the output of the first element I, the output with the recording input of the reversible pulse counter and the S input R5 of the trigger, whose R input is connected to the output of the third element I, the first input of which is connected to the output of the zero decoder code, and the second input - with the output of the second element, And, the second input of which is connected to the second output of the pulse generator, and the output of the setting unit of the code is connected to the input of this unit to a 1 reversible pulse counter.

Description

The invention relates to a pulse technique and can be used in control and automation measurement devices for isolating pulse signals against a background of interference.

A device for selecting pulse signals is known, comprising a pulse counter, a pulse generator, a trigger, three AND elements, an OR element, and two 1 J inverters,

A disadvantage of the known device is low noise immunity.

The closest to the technical essence of the invention is a device for selecting pulse signals, which contains a reversible pulse counter, the summation inputs and the subtraction of which are connected to the outputs of the first and second elements, respectively, and the bits of the outputs of the zero code decoder and the first inputs of the comparison element, the second the inputs of which are connected to the output of the master code, the inverter, the output of which is connected to the first input of the second element AND, the input to the input pin and the first input of the first element AND, W The open input of which is connected to, the output of the pulse generator, the third element And, the output of which is connected to the input of the installation in the zero state of a reversible pulse counter, the RS flip-flop (straight) 5 whose code is connected to the output pin and to the second input of the second element And , 5-input to the output of the comparison element, .R-input to the output of the zero-code decoder, the inverse output to the third input of the first element And the second input of the third element And, while the output of the pulse generator is connected to the third input of the second element And 23.

The disadvantage of the famous; The device is its low noise immunity, due to the fact that short interference pulses reset the pulse counter to its original state.

The purpose of the invention is to improve noise immunity.

The goal is achieved by the fact that in a device for selecting pulse signals containing a reversible pulse counter, the summation and subtraction inputs of which are connected to the outputs of the first and second elements, respectively, and

the outputs of bits are to the inputs of the zero-code decoder and the first group of inputs of the comparison element, the second group of inputs of which is connected to the outputs of the setpoint generator, the inverter, the output of which is connected to the first input of the second element And, the input to the input bus and the first input of the first element And the second input connected to the first output of the pulse generator, the third element And, the output of which is connected to the input of the reversing pulse counter in the zero state, R5-flip-flop, the output of which is connected to the output bus, entered four first AND gate having a first input coupled to the output of the comparison element vtrroy input - with

the output of the first element I, the output with the recording input of the reversible pulse counter and the 5 input of the Rs-flip-flop, the R-input of which is connected to the output of the third element I, the first input of which is connected to the output of the zero-decoder. yes and the second input is with the output of the second element I, the second input of which is connected to the code of the pulse generator, the output of the code setter is connected to the data input of the reversing pulse counter.

Figure 1 shows the functional diagram of the device;

FIGS. 2 and 3 show the operation of the device in the absence and in the presence of interference; a and b are voltage diagrams at the input and output of the device, S are state diagrams of the device counter.

The device contains a pulse generator 1, the first, second, third and fourth elements AND 2-5, Rs-flip-flop 6, the reversible counter of 7 pulses, the setpoint generator code 8, the element of comparison 9, the decoder zero 10

code and inverter 11.

The first input element And 2 is connected to the input bus and through the inverter

11 to the first input element FROM. The first and second outputs of the generator 1 are connected to the second inputs of the elements 2 and 3, respectively. The output of the element 2 is connected to the input

from pimirovaniya counter 7 and the second input element And 5. The output element And 3 is connected to the subtraction input of counter 7 and the second input element 3

This and 4. The outputs of the bits of the counter 7 are connected to the first group of inputs of the comparison element 9 and the decoder 10, the outputs of which are connected to the first inputs of the And 5 and 4 elements, respectively. The output of the code setter 8 is connected to the second group of inputs of the comparison element 9 and the data input counter 7. The output of the element And 4 is connected to the R-input of the ps-trigger 6 and the installation input to the initial state of the counter 7. The output of the element And 5 is connected to the 5-input of the RS-flip-flop 6 and the recording input of the counter 7. The output of the RS-flip-flop b.podklyuchey to the output bus.

The principle of selection of the input pulse signal X in the proposed device is described by the expression of G 1 at N

, (one)

oh for um um

i nts-p

Vnn

where to

.

С I к - respectively, the duration, the selection setpoint and the weighting factor of the pulse width of the input signal;

fj. , Kf, - respectively, the duration, the selection setpoint and the weighting factor for the duration of the pause of the input signal}

n is the number of alternations of pulses and pauses of the input signal.

(2)

In accordance with the extrusion (2), the decision on the equality of the input signal to a unit is made if for a certain number of n interlaces of pulses

ow and pauses, the sum of the pulse durations of the input signal becomes, with not less than a setpoint value greater than the sum of the durations of pauses 5 of the input signal, and the decision on equality of the input signal to zero is taken if for a certain number of pulses and pauses alternations the sum of pauses of the input signal sfO becomes no less than the set value is greater than the sum of the pulse durations of the input signal. When, the device works in accordance with the expression (1) that

15 allows, for example, when K. K ,, to decide on the presence of a pulse at the input of the device, with a predominant intensity of interference, causing signals to pause.

20 The weighting coefficients of pulse durations and pauses are set by the frequencies f,

and

-oi

01

generator 1 pulses, and Cc fcoi, and K „fo2. Operations

I comparison of the weighted durations is carried out using the counter 7 with the capacity M, the input of which receives the setpoint code; N с i M output of the setter 8.

In accordance with the above, the device operates in the following manner (Fig. 2a, C). , -.

The input signal X is a sequence of square pulses () alternating with pauses (). Pulses and pauses of the input signal, i.e. the signal X and its inversion X, which is formed at the output of the element of the inverter 11, is subjected to separate quantization (weighting), respectively, using the elements I 2 and I 3 due to the impact on them of pulses 1. At the same time, when X 1,

at the output of the element And 2, pulses of frequency f are formed, the number N p, which is proportional to the pulse duration L, of the input signal

i-foi ni,

and when X O, the output of the element I 3 produces pulses of frequency f 02 the number N ", which is proportional to the pause of the input signal.

.

5 Accordingly, with the alternation of pulses and pauses of the input signal, at the outputs of the And 2 and And 3 elements, the sequences and the number of pulses are formed in proportion to the total value of the weighted Pulses and Pauses. For simplicity, let fi, fo. fg. Then the selection setting of the pulse duration is equal to the selection setting of the pause duration, i.e. . , Let the pulse duration f and the pause duration of the input signal satisfy the conditions and p. &Amp; (. Then, when the pulse of the input signal appears, the number of pulses formed at the output of the And 2 element does not reach the interval V, N, ... Under the influence of these pulses, the counter 7 successively enters a state with a monotonously increasing number N- and has time to be set to state N .N. At this moment, the comparison element 9 is triggered and at its output a signal appears that unlocks the AND 5 element. The next pulse forms a out The element 2 and passes through the element 5 and is passed to the 5 input of the counter (FIG. 2b) and to the S input of the RS trigger of 6. At the same time, the number Nj is written to the counter 7 and, therefore, its state is not changes, and a single signal is set at the output of the Re-flip-flop 6. The occurrence of the last means that a decision is taken on the presence of a pulse at the device input () Respectively on the interval f, the number of pulses formed in the reading input of the counter 7 reaches NL, N. .. Counter 7 of the last Ml waffle enters the state with the monotonously kill number NJ. At time N.0, the decoder 10 is triggered and generates a signal unblocking element I 4. The next pulse generated at the output of the IZ element passes through element 4 and enters the f-input of the counter 7 and the R input of the RS flip-flop 6, Pr therewith, the counter 7 is set to the zero state, i.e. its state does not change, and a zero signal is set at the output of the RS flip-flop 6. The appearance of the latter means that a decision is made about the presence of a pause () at the device input. Thus, at the output of the device, a sequence of pulses (pauses) is formed, the length of cots) is equal to the duration of the corresponding input pulses (pauses). At the same time, the output pulses (pauses) are delayed relative to the input pulses (pauses) for a time equal to the setting of the duration of T G. (fig.2, Sv). Let now, due to interference, one of the pulses of the input signal from the moment of its formation is interrupted (Drobits) with short pauses. As a result, with each pulse occurrence of the sequence N, the monotonous nature of the growth of the number N., which characterizes the state of the counter 7, is violated. If after a certain time interval, the total value of the pulse durations at the device input, resulting from the pulse splitting. The input signal with interference - pauses, exceeds the sum of the Durations of these pauses by a time equal to the selection threshold with | Then the difference in the number of pulses reaching the inputs of counter 7 reaches the value Nj- Then counter 7 has time to install. to the extreme state, and at the output of RS - flip-flop 6, a single signal is inserted. HMnyjjbCj, which is formed at the output of the device, a), is delayed relative to the input at the time. The delay is greater, the greater the intensity of interference. . Suppose now that, due to interference, one of the pauses of the input signal, since its formation, is interrupted (crushed) by short pulses. As a result; the monotonous nature of decreasing N. is violated. A zero signal at the output of the 5-flip-flop 6 yciia becomes impacted if after a certain interval of time the difference in the number of pulses entering the inputs of counter 7 reaches the value of Kp, and the counter 7 has time to set to the state N. 0. Pause for the device lags relative to the pause of the input signal at the time. Splitting is greater, the greater the intensity of interference. Thus, the introduction of the fourth element And and new connections in | y7 1129 favorably distinguishes the proposed device from the prototype, since it allows to ensure the selection of pulse signals when exposed to interference, which causes the pulse splitting (power 727 ee) of the input signal into parts, even if the duration each part is less than the selection setpoint, i.e. improve noise immunity.

fPUi.f

2

Fig.Z

Claims (1)

DEVICE FOR SELECTION OF PULSE SIGNALS, containing a reversible pulse counter, the summing and subtracting inputs of which are connected to the outputs of the first and second I elements, respectively, and the discharge outputs to the inputs of the zero code decoder and the first group of inputs of the comparison element, the second group of inputs of which are connected to the outputs of the setter code, an inverter, the output of which is connected to the first input of the second AND element, the input is to the input bus and the first input of the first AND element, the second input of which is connected to the first output Pulse ring, the third AND element, the output of which is connected to the zero setting of the reversible pulse counter, an RS-trigger, the output of which is connected to the output bus, characterized in that, in order to increase noise immunity, a fourth And element is inserted into it, the first input which is connected to; the output of the comparison element, the second input is the output of the first AND element, the output is the recording input of the reversible pulse counter and the S-input SS house of the R5-trigger ,. The R-input of which is connected to the output of the third element of ¹ AND, the first input of which is connected to the output of the decoder of the zero I code, and the second input is with the output of the second S element of the And, the second input of which is connected to the second output of the generator pulses, and the output of the code master is connected to the data input of the reversible pulse counter. ί