RU1824669C - Pulse length selector - Google Patents

Abstract

The invention relates to pulse technology and can be used in automation devices and in measurement technology. The inventive device comprises a reference pulse generator 1, AND elements 2 and 3, a pulse counter 4, a decoder 5 zero, a code comparison unit 6, a trigger 7, an inverter 8 and a key 9. Provision, start possibilities; the formation of the output pulse at the moment when the duration of the input pulse reaches the selection threshold, it improves the speed in the selection mode of pulses of maximum duration. 2 ill.

Description

input

-

Ј

Mode controls

Vn P

g

-g

Output

00

Yu

oh oh

H

7

Figure 1

The invention relates to pulsed technology and can be used in computing and measuring devices to isolate and account for pulsed signals whose duration is less than or greater than a predetermined limit.

The purpose of the invention is to increase the speed in the selection mode of pulses of maximum duration by providing the possibility of the beginning of the formation of the output pulse when the duration of the input pulse reaches the selection threshold.

Figure 1 shows the structural electrical circuit of the device; figure 2 - timing diagrams of the operation of the device.

The device comprises a reference pulse generator 1, elements And 2 and 3, a reverse counter 4, a decoder zero 5, a code comparison unit 6, a trigger 7, an inverter 8, an electronic key 9.

The device operates as follows.

In the pulse width selection mode of minimum duration, the D-input of trigger 7 is connected to the output of the code comparison unit 6, input S of trigger 7 is connected to the power bus.

In the initial state, the counter 4 and the trigger 7 are in the zero state.

Upon receipt of a pulse at the input of the device (Fig.2-1 b) the level of the log. 1, the And 3 element opens, allowing the passage of pulses from the generator 1 to the summing input of the counter 4.

Element I2 is closed by a log level. O from the output of inverter 8, prohibiting the passage of pulses from the generator to the subtracting input of the counter 4.

If the duration of the input pulse is less than the selection threshold, then by the time the pulse ends, the code in counter 4 will be less than the selection threshold and a difference from the log level. About 1 from the output of inverter 8, which goes to the C-input of trigger 7, it is set to a single state ( 2-1 g), because at its D-input, the level is log. 1 from the code comparison unit 6 (Fig. 2-1 a). By log level 1, the I2 element opens from the inverter 8 output, allowing the passage of pulses from the generator 1 to the subtracting input of the counter 4. The log.O level closes the IZ element from the input of the device. At the time when the counter 4 is in the zero state, at the output of the decoder 5 (Fig. 2-1 c), the log level O., which, entering the trigger input R, returns it to the zero state, is received on element I2 closes it, prohibiting the passage of pulses from generator 1 to the subtracting input of counter A.

At the direct output of trigger 7, a pulse of duration equal to the input will be generated.

If the duration of the input impulse

is greater than the selection threshold (Fig. 2-1 e), then when the counter 4 reaches a code equal to the selection threshold, the output of the code comparison unit 6 will show the log level O. (Fig. 2-1 a), which will close the FR element, prohibiting the passage of pulses from generator 1 to the summing input of counter 4. At the end of the pulse at the input of the device, a difference from the log level. About 1 from the inverter 8 output to the C-input of trigger 7 confirms its zero state, because at its D-input there is a log level. O from the code comparison unit 6, i.e. at the direct output of trigger 7, no pulse is generated (Figs. 2-1 h). Log level 1 from inverter 8 allows

0 the passage of pulses from the generator 1 through the I2 element to the subtracting input of the counter 4. When the counter 4 is in the zero state, the log level.O from the output of the decoder 5 (Fig.2-1 g) will close the I2 element,

5 prohibiting the passage of pulses from generator 1 to the subtracting input of counter 4. In the pulse selection mode of maximum duration (see Fig. 2-11), the D-input of trigger 7 is connected to a common bus, and

0 S-input - to the output of the code comparison unit 6. The device operates as described.

Moreover, if the duration of the input pulse is less than the selection threshold, then by

5, only the zero state of trigger 7 is confirmed, i.e. the pulse at the direct output of the trigger 7 is not formed (Fig.2-11 d, g, h), if the duration of the input pulse is greater than the selection threshold, then when

0 when the code on counter 4 is equal to the selection threshold, at the output of the code comparison unit 6, the log level O. (Fig. 2-11 a), which closes the FR element and arrives at the S-input of trigger 7, sets it in a single state (Figs. 2-11 g).

At the end of the input pulse, the flip-flop of the trigger 7 to the zero state does not occur, although its D-input has a logic level O. at this time, at its S-input level log. O from the output of the code comparison unit 6.

The pulses from the generator 1 begin to arrive at the subtracting input of the counter 4 through the open element And2. When counter 4

5 will be in the zero state, the log level. O from the output of the decoder 5 will overturn the trigger 7 to the zero state and close the I2 element, thus, a pulse will be generated at the direct output of the trigger 7, different in duration similar.

Claims (1)

SUMMARY OF THE INVENTION A duration pulse selector comprising a reference pulse generator, the output of which is connected to the first inputs of the first and second elements AND, the outputs of which are connected respectively to the subtracting and summing inputs of the pulse counter, the outputs of which are bitwise connected to the inputs of the first group of inputs of the code comparison unit, the inputs of the second group of inputs of which are connected to the selection threshold bus, and the output - with the first information input of the electronic key, the first output of which is connected to the trigger D-input the output of which is connected to the output bus, and the R-input is the output of the decoder, the inputs of which are bitwise connected to the outputs of the pulse counter, as well as an inverter, input bus, and mode control bus, characterized in that, for the purpose of {lopoz I p increasing the speed in the mode of selection of pulses of maximum duration by providing the possibility of the beginning of the formation of the output pulse at the moment the duration of the input pulse reaches the selection threshold, the input bus is connected to the second input of the second element And with the input of the inverter, the output of which is connected to the second input of the first element And and with a trigger C-input, the S-input of which is connected to the second output of the electronic key, the second information input of which is connected to the potential bus of the logical unit, 15 third information input - with a common  bus, and control input - with bus control mode, and the third input the first element AND is connected to the output a decoder, and the third input of the second element And - with the output of the code comparison unit. impumsob selection bench