SU1120334A1 - Signature analyzer with variable structure - Google Patents

Abstract

A SIGNATURE ANALYZER WITH A REJECTABLE STRUCTURE, containing a modulo two and four shift nodes, each of which contains a shift register, a decoder and a display node, and in each shift node the shift register outputs are connected to the decoder inputs, whose outputs are connected to the display node inputs, the first input of the modulo two adder is the information input of the analyzer, the direct output of the third bit of the shift register of the second node, the shift, the direct outputs of the first and fourth bits of the shift register, the third The node of the shift and the direct output of the fourth bit of the shift register of the fourth node of the shift are connected respectively to the second, third, fourth and fifth inputs of the modulo-two adder, characterized in that, in order to expand the analyzer's functionality by providing control blocks, having tight synchronization, two switches are introduced into each shift node, four AND elements and an OR-NOT element, with the inputs of the first AND element in each shift node connected to the inverse outputs of the first and second, respectively and the third bit and with the direct output of the fourth bit of the shift register, the inputs of the second element And are connected respectively to the direct output, the third and inverse output of the fourth bit of the shift register, the inputs of the third element And are connected respectively to the inverse output of the first and direct the output of the second bit of the shift register, the inputs of the fourth element I are connected respectively with the inverse output of the third and the direct output of the fourth (L of that bit of the shift register, the outputs of the second, third and fourth elements And soi Dineny with the corresponding inputs of the element OR NOT, the output of which is connected to the first information input of the first switch, the outputs of the first and second switch d are connected respectively to the information and shift inputs of the shift register, the control inputs of all the switches of all nodes are combined and have J the analyzer operation mode input, the output of the modulo two adder is connected to the second information input of the first switch of the first shift node, the first information input of the second switch of the first node the shift is connected to the information input of the analyzer, and the direct output of the fourth bit of the shift register and the output of the first element AND of each node shift

Description

the input of the second commutator of all the shift nodes is

mutator (p) -th node shift g

JBTopbie information inputs second

1120334

single and are the analyzer sync input

The invention relates to automation of computing and instrumentation technology and can be used to monitor and diagnose digital devices. A signal analyzer that contains a shift register is known modulo two C1. The disadvantage of this analyzer is the impossibility of operating without synchronization signals. The closest to the invention according to the technical essence is a full-scale analyzer containing four functional cells according to the number of signature indicators and a modulo-two adder, the first input of which is the measuring input of the signature analyzer, each functional on the cell contains a four-bit shift register, outputs through which the decoder is connected to the indicator, the shift registers of the functional cells are connected in series to the 16-bit shift register, the outputs of the seventh, ninth, twelve The second and sixteenth bits of which are connected respectively to the second, third, fourth and fifth inputs of the modulo two adder, the output of which is connected to the information input of the C 2 1 shift register. However, the known analyzer does not allow the counting of pulses in controlled electric circuits and accordingly, it cannot be used to diagnose digital devices using the transient counting method, i.e. The scope of application of the known analyzer is limited by the ability to control digital circuits having rigid synchronization (synchronous circuits) and having previously compiled signature patterns in the documentation system. The purpose of the invention is to expand the functional capabilities of the analyzer by providing control units that do not have tight synchronization. The goal is achieved by the fact that in a signature-based analyzer with a tunable structure that contains a modulo two and four shift nodes, each of which contains a shift register, a decoder and a display node, and in each shift node, the outputs of the shift register are connected to the decoder inputs, the outputs of which are connected with the inputs of the display unit, the first input of the modulo-two adder is the information input of the analyzer, the direct output of the third bit of the shift register of the second shift node, the direct outputs of the first and the fourth The third offset node's shift register bits and the direct bit of the fourth bit of the shift register of the fourth shift node are connected respectively to the second, third, fourth, and fifth modulo-two inputs, two switches, four elements, and an element are entered into each shift node. OR NOT, and in each node shift the inputs of the first element. And are connected respectively to the inverse outputs of the first, second and third bits and to the direct output of the fourth bit of the shift register inputs of the second element And are connected respectively to the direct output of the third and inverse output of the fourth bit of the shift register, the inputs of the third element And are connected respectively to the inverse of the first and the direct output of the second bit of the shift register; the inputs of the fourth element H are connected respectively with the inverse of the third and direct output of the fourth bit of the register The motor, outputs of the second, third and fourth elements AND are connected to the corresponding inputs of the OR-NOT element, whose output is connected to the first information input of the first switch, the outputs of the first and second switches are connected respectively to the information and shift inputs of the shift register, the control inputs all the switches of all the nodes of the shift are connected and are the analyzer's mode of operation; the output of the modulo two adder is connected to the second information input of the first switch of the first node of the shift, The first information input of the second switch of the first shift node is connected to the information input of the analyzer, and the direct output of the fourth bit of the shift register and the output of the first And element of each nth shift node (3) are connected respectively to the second information input of the first switch and the first information the input of the second switch (n + 1) -th node of the shift; the second information inputs of the second switch of all the nodes of the shift are combined and are the sync input of the analyzer. FIG. 1 shows a functional diagram of a signature analyzer with a tunable structure; in fig. 2, - table of the truth of the decoder; in fig. 3 - table shift register transitions in counter mode. The signature analyzer with a tunable structure (Fig. 1) contains an adder 1 modulo two, nodes 2 addr, composed of a shift register, decoder 4, display unit 5, elements 6–9, switches 10 and 11, element OR-NOT 12, the second information input 13 of the first switch, information inputs 14 and 15 of the second switch, controlling input 16 of the first switch, output 17 of the first element AND 6, direct outputs 1820 of the first, third and fourth bits of the shift register, information input input 21 of the analyzer, input 22 of the analyzer synchronization, input 23 Modes of operation of the analyzer. The sign Z denotes a hexadecimal code displayed by the display node 5. The first input of the modulo two adder is the information input of a 21 sig- nal analyzer, and the second, third, fourth, and fifth inputs of the adder 1 modulo two are connected respectively to the direct output of the third bit of the shift register of the second shift node, the direct outputs of the first and fourth bits of the third node shift and direct output of the fourth bit of the fourth node shift. The outputs of the first element And 6 and the fourth bit of the register 3 shift of the first, second and third nodes 2 shift are connected respectively to the first information input of the second switch and the second information input of the first switch of the second, third and fourth nodes 2 shift. The input 23 of the analyzer operation mode is connected to the control inputs of the switches of all shift nodes. The outputs of the shift register 3 of each node 2 shift are connected via a decoder 4 from the display node 5. The inverse outputs of the first, second and third bits of the shift register 3 are connected respectively to the first, second and third inputs of the element 6, the fourth input of which is connected to the output of the fourth bit of the shift register 3. The shift register 3 can be built on series-connected D-flip-flops, the synchronization inputs of which are combined. The decoder 4 is a combination circuit whose truth table is shown in FIG. 3, it can be implemented on any logic elements. Any indicator that can display an hexadecimal code, for example, a seven-segment AJI312A indicator, can be used as an indication node 5. The signature analyzer with a tunable structure allows the formation of signatures (compression) of controlled sequences in accordance with the shift register feedback polynomial, as well as counting pulses in controlled circuits, displaying the counting result in decimal code, or checking transient counting sequences. The signature analyzer is connected with its information input to the monitored circuit, and the synchronization input is connected to the output and 1 synchronization pulses of the monitored device. Signature analyzer with a tunable structure works as follows. A signal is applied to the input of the device operation mode, which sets the signature generation mode of the controlled sequences or the pulse counting mode. In the first mode, the zero potential voltage sets the switches 10 and 11 to the state corresponding to the transfer of information from the second information inputs to the outputs. The TatKoe state of the switches corresponds to the transmission of a feedback signal generated modully 2 at the output of adder 1, through the switch 10 of the first shift node 2 to the information input of the shift register 3, transferring information from the outputs of the fourth bits of the first, second and third shift registers 3 2shift nodes to the information inputs of the 3 shift registers, respectively, of the second, third and fourth shift nodes 2 through the switches 10 and transmitting the synchronization signal to the input 22 of the signature analyzer via the second mmutators 11 nodes 2 shifts to the shift inputs of 3shift registers. Modulo 1 modulo two, the inputs of which receive signals from the third bit of shift register 3 of the second shift node 2, from the first and fourth bits of shift register 3 of the third shift node 2, and from the fourth bit of shift register 3 of the fourth shift node 2, generates a modulo sum of these two signals with the superimposed on it of a controlled signal arriving at the information input 21 of the signature analyzer. Formed by adder 1 modulo two, the sum corresponds to the sum modulo two signals taken from the seventh, ninth, twelfth and sixteenth bits 1b-bit of the shift register formed by a series connection of 4 shift registers of the shift node 2, i.e. . The signature analyzer generates a signature (compression) of the monitored sequence in accordance with the polynomial ObR (X) of the tied links + 1. In the second mode, a single signal is fed to the control inputs of the switch 10 and 11 ysjrioB 12 shift. which sets them to the state corresponding to the transmission to their outputs of signals from the first information inputs. This state of the switches 10 and 11 corresponds to the transfer of the monitored signal to the shift input 346 of the shift register 3 of the first shift node 2, transfer of the transfer signals, the formed elements And 6 of the first, second and third shift nodes 2 to the shift inputs of the shift registers of the second, third and the fourth nodes 2 shift and transfer in each node 2 the shift of the feedback signal formed by the element ILINE 12 from its output through the switch 10 to the information input of the shift register 3. The organization with the help of switches 10 and 11 of the indicated switching of signals allows the signature analyzer to be restructured so that each node 2 of the shift represents a divider by ten frequencies of the signal fed to the first information input of the second switch 11. The mode of division by ten frequencies of the input signal on the four-bit shift register 3, feedback is provided to the information input of the shift register 3 from the outputs of the second, third, and fourth elements AND 7-9 through the OR-NOT 12 element. their elements realizes a function of input variables Q, ..., Q, and provides the order of transitions in the shift register 3 dividing mode for ten (FIG. 3). Element And 6 generates a carry signal for high order dividers. At its output, the VIT signal of the logical O is only in the case when the shift register is set to the Q O, Q O, Q O, Q 1 state, i.e. after arriving at the shift input of the register 3 shift nine pulses. After the tenth pulse arrives at the shift register, its state changes, and a high logic level is set at the output of element 6. The transition of the state | at the output of the element And 6 from a low logical level to a high one, arriving at the shift inputs of the shift registers 3 of the next nodes 2 shift. and is a transfer signal. Thus, in the second mode, the signature analyzer is rebuilt in such a way that its 2 shift nodes form four successively connected dividers by ten, that is, signature analyzer in this mode can be used in ka71

the tenth pulse counter.

The decoder 4 nodes 2 shift in both modes converts the state of the register 3 shift to digital signals of the seven-segment code, providing the flashing of numbers and letters on the seven-segment digital display. Transformed on the decoder 4 states / J / "15

111.

203348

The shift register 3 is indicated by the display nodes 5 in decimal code in pulse counting mode (Fig. 2), in hexadecimal code 5 in signature generation mode (Fig. 3). Thus, the proposed signature analyzer allows counting pulses.

nineteen

one

2

20 figure 1

Figg

fig.Z

Claims (1)

A SIGNATURE ANALYZER WITH A TUNABLE STRUCTURE, comprising an adder modulo two and four shift nodes, each of which contains a shift register, a decoder and an indication node, and in each shift node the outputs of the shift register are connected to the inputs of the decoder, the outputs of which are connected to the inputs of the indication node, the first modulo two adder input is the analyzer information input, direct output of the third bit of the shift register of the second node. · shift, direct outputs of the first and fourth bits of the shift register of the third node the motor and direct output of the fourth category of the shift register of the fourth shift node are connected respectively to the second, third, fourth and fifth inputs of the adder modulo two, characterized in that, in order to expand the analyzer's functionality by providing control of units that do not have tight synchronization, each switch node has two switches, four AND elements and an OR-HE element, and at each shift node the inputs of the first AND element are connected respectively to the inverse outputs of the first, second, and third discharge s and with direct output. the fourth bit of the shift register, the inputs of the second element And are connected respectively to the direct output, the third and inverse outputs of the fourth bits of the shift register, the inputs of the third element And are connected respectively to the inverse output of the first and direct output of the second bits of the shift register, inputs of the fourth element And are connected respectively with the inverse output of the third and direct output of the fourth bits of the shift register, the outputs of the second, third and fourth elements And are connected with the corresponding by the moves of the OR-HE element, the output ι of which is connected to the first information input of the first switch, the outputs of the first and second switches are connected respectively to the information and shift inputs of the shift register, the control inputs of all the switches of all nodes are combined and are the input of the analyzer operating mode, the output of the adder is module two is connected to the second information input of the first switch of the first shift node, the first information input of the second switch of the first shift node is connected to the information input lyser, and the direct output of the fourth category of the shift register and the output of the first AND element of each nth shift node (1 4p .. <3) are connected respectively to the second information input of the first switch and the first SU „„ 1120334 by the information input of the second commutator of all the nodes of the switch of the switch (n + 1) of the node of the shift, the synchronous information inputs of the second analyzer are unified and are the input.