JP3052691B2 - Pulse phase difference encoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a phase difference between two pulse signals having an arbitrary phase relationship.
In particular, the present invention relates to a pulse phase difference encoding circuit capable of detecting a very high accuracy over a wide range.

[0002]

2. Description of the Related Art Conventionally, a pulse phase difference encoding circuit (time A / D conversion circuit) for converting two pulse phase differences (pulse time differences) into codes (numerical values) is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-220.
No. 814 proposes. That is, a plurality of delay elements are connected in a ring shape, a first pulse input at an arbitrary timing is circulated, the number of laps is counted, and an input of a second pulse input with an arbitrary phase difference is input. The position of the first pulse that corresponds to the timing is specified, and the phase difference between the two pulses is detected based on the specified position and the count number.

[0003]

However, in the above-described conventional pulse phase difference encoding circuit, it takes time for the output of the counter to stabilize in the counter that counts the number of times the pulse circulates (hereinafter, this time is referred to as the time period). In this case, two counters are used because it is necessary to select a stable output. That is, while the first pulse makes one rotation, the output state of each counter is shifted so that one of the counters becomes a stable output by one half rotation.
The stable output is obtained. And this counter needs a circuit to be its clock,
Each counter is provided with one clock circuit. For this reason, counting must be performed at two places, and the arrangement of the circuits becomes complicated, or the wiring from each counter to a circuit for selecting a stable output of these counters, etc. It is supposed to increase the area.

Accordingly, it is an object of the present invention to provide a pulse phase difference encoding circuit capable of counting the number of revolutions at one place.

[0005]

That is, in order to solve the above-mentioned problem , in the invention according to claim 1, an arbitrary tag is set.
The pulse PA input at the time of
And the position of the pulse PB input with an arbitrary phase difference
Pulse phase difference encoding circuit that encodes the phase difference
In the multiple signal delay circuits, the final output stage
To return to the signal delay circuit of
Delayed by the delay time of the signal delay circuit in the signal delay circuit
The signal that passed this pulse PA
Multiple delay pulses sequentially delayed by the delay time of the delay circuit
And the ring delay pulse generating circuit repeatedly generates the
The delay pulse of the ring delay pulse generation circuit is input.
And a plurality of input lines corresponding to the delay pulse.
And the input timing of the pulse PB
The ring delay pulse in a specific time relationship
According to the state of the delay pulse from the generation circuit, the output is
A pulse selector for changing the state of the power line, the pulse
The output from the output line of the selector is input and the
Digital corresponding to the state of the output line of the pulse selector
An encoder for outputting a signal, the ring delay pulse onset
Including the same signal delay circuit as the signal delay circuit of the raw circuit
Generated by the ring delay pulse generation circuit
Two paths inverted from each other based on one of the delay pulses
A pulse generator for outputting a pulse signal, the pulse
Upon receiving one pulse signal of the generator,
The pulse PA circulates in the ring delay pulse generation circuit.
A first counter for counting the number of rotations,
Upon receiving the other pulse signal of the generator,
The pulse PA circulates in the switching delay pulse generation circuit.
The number of revolutions is less than the count timing of the first counter
A second counter for counting Rashi, the encoder
The first counter and the second counter depending on an output state
And the pulse PA is set to the ring delay.
A digital signal that indicates the number of revolutions in the pulse generation circuit
And a selection circuit for deriving a guide by the selection circuit
The output digital signal and the digital output from the encoder
The position of the pulse PA and the pulse PB is determined by the
A phase difference code representing a phase difference is obtained . Further, in the invention described in claim 2,
1, the ring delay pulse generating circuit
Of individual signal delay circuits in the delay circuit
The input units respectively connected to the lines and the pulse selector
Output unit connected to each input line.
A plurality of second signal delay circuits, and the second signal delay
A second circuit having an input and an output connected to the output of the circuit;
3. The pulse generator according to claim 1, further comprising:
Is the same as that of the ring delay pulse generation circuit
Signal delay circuit, second signal delay circuit, and third
A ring delay pulse comprising a signal delay circuit;
One output section of the third signal delay circuit included in the generation circuit
The ring delay pulse connected to the pulse generator
One of the delay pulses generated from the
It is characterized in that it is inputted to a generator. Also, billing
In the invention described in Item 3, the plurality of signal delay circuits are linked.
The first signal that is concatenated and input is
Delay of individual signal delay circuits within multiple signal delay circuits
The circuit rotates while being delayed by the time, so that the first signal is transmitted.
Multiple delay signals delayed by the delay time of the
Signal generation means for repeatedly generating a signal ,
A second signal having a phase difference from the signal is input, and the second signal
When a signal is input, the plurality of signal delay circuits
Position detecting means for detecting the orbiting position of the first signal
And one between the plurality of signal delay circuits connected in a ring.
And after the first signal is input
By the time the second signal is input, the first signal is
Counts the number of rounds in multiple signal delay circuits
And the first signal is the same circuit and
Selectively toggle used before and after passing through the serial one connection point
First Bei the counting means and the second counting means is
For example, the second signal is selected in the inputted timing
By the first counting means or the second counting means.
The number of turns of the first signal to be transferred and the position detection
Means for circulating the first signal detected by the means
A position between the first signal and the second signal
The phase difference is encoded. Also,
In the invention according to claim 4, in claim 3,
The delay signal generation means includes an individual in the delay signal generation means.
An input section and the position respectively connected between respective signal delay circuits;
A plurality of second signals having an output connected to the detecting means.
Signal delay circuit and respective output sections of the second signal delay circuit
Signal delay with input and output connected to
And the same circuit as the delay signal generating means.
Signal delay circuit, second signal delay circuit, and third signal delay circuit having the same configuration.
And the one connection
A second signal delay circuit of the delay signal generation means at a continuation point;
And via the third signal delay circuit,
Generated based on delayed signals generated from two connection points
One of the different signals is sent to the first counting means and the other signal is sent to the first counting means.
Signal generating means for inputting the signals to the second counting means.
It is characterized by having. The invention according to claim 5
In the following, a plurality of signal delay circuits are connected in a ring shape,
One pulse PA input at an arbitrary timing is
Circulates in a plurality of linked signal delay circuits and
The number of laps is counted, and the pulse PA
For the input timing of the pulse PB input with a phase difference
Identify the corresponding orbital position of the pulse PA and specify the
According to the position and the count number, the two pulses PA and
A pulse phase that encodes the phase difference of the pulse PB
In the differential encoding circuit, a plurality of
Based on the output signal at the predetermined position of the signal delay circuit,
The first cow that counts the number of times the pulse PA circulates
At the same position as the predetermined position of the signal delay circuit.
Number of revolutions of the pulse PA based on the output signal
Less than half a turn from the count timing of the first counter
A second counter for counting the pulse PB
At the orbiting position of the pulse PA corresponding to the input timing
Therefore, either the first counter or the second counter
And a selection circuit for selecting, input type of the pulse PB
Circulating position of the pulse PA corresponding to the
The first counter or the second counter selected by the circuit
The pulse PA and the pulse PA
To obtain a phase difference sign representing the phase difference from the pulse PB
It is characterized by having done. Further, according to the invention of claim 6,
6. The individual signal delay circuit according to claim 5,
A plurality of first units having an input unit and an output unit respectively connected therebetween.
2 signal delay circuit and the second signal delay circuit
A third signal having an input connected to the output and an output.
A delay signal generator means having a No. delay circuit, the delay signal
Signal delay circuit having the same configuration as that of the signal generation means and
Including a second signal delay circuit and a third signal delay circuit
And the delay at a predetermined position of the signal delay circuit.
The second signal delay circuit of the signal generating means and the third signal delay circuit
Connected through a signal delay circuit, and connected to the signal delay circuit.
Different signals generated based on the output signal at the fixed position
One of the signals to the first counter and the other signal to the second counter.
Signal generating means for inputting the signals to the
You.

[0006]

According to the pulse phase difference encoding circuit of the present invention, a plurality of signal delay circuits connected in a ring (annular) are provided.
The number of laps of the pulse PA (first signal) circling the road is increased by
In one place between the signal delay circuits, two
First and second counters (first counting means, second counting means
Means), counting by shifting the count timing,
The first counter and the second counter are selectively used.
In one place, counting the number of laps
A possible pulse phase difference encoding circuit can be realized. As a result, the arrangement of each counter which has been conventionally seen, or
Problems such as wiring routing can be solved.

[0007]

FIG. 1 shows a specific first embodiment of the configuration of the present invention. The time difference between the pulse input to PA and the pulse input to PB is measured. g00
Are two-input NAND circuits, g01 to g62, g
000 to g620 and g001 to g621 indicate inverter circuits. The output of g00 is input to g000 and g01. The output of g01 is input to g010 and the next stage. The output of the g010 is input to g011 and D-type flip-flop d1. g01, g010, g
A circuit in which three inverters 011 are connected as shown in FIG. The delay element cells are repeatedly connected in 62 stages, and the output of g62 is connected to the 2-input NAN.
The signal is input to one side of the D circuit, and the input signal PA is input to the other side. The circuit connected in 63 stages in this manner is referred to as a ring delay pulse generation circuit 10. The signals output from g000 to g620 of the ring delay pulse generation circuit 10 are 63 D-type flip-flops d0 to d of the pulse selector 20.
62 is input. The clocks of these flip-flops are the input signals of PB. ER00 to ER62 are EX
This is an OR circuit. ER01 receives the output signals of d0 and d1, and ER02 receives the output signals of d1 and d2, which are sequentially input to 63 EXOR circuits.
63 output signals from the pulse selector 20 are input to the encoder 30 and are 6-bit data (EC1 to 6).
Is converted to G3 in the ring delay pulse generation circuit 10
The output signal from 11 is input to the inverter circuit in the pulse generator circuit 40. The output of the inverter circuit is the input of the EXOR circuit and the inverter circuit p01.
Is input to p01 to p32 are delay element cell 1
The same circuit is used to construct a 32-stage delay element cell.
To achieve . The output of p32 in the 32nd stage is the output of the EXOR circuit .
It is input as another input signal . Then, the output becomes the clock of the 10-bit counter 1 (50). The inverted signal of the EXOR circuit becomes a clock of the 10-bit counter 2 (51). RS is a reset signal for the two counters, and both the counters 1 and 2 are reset to 0.

The outputs of the two counters are input to two D-type flip-flops 60 and 61, and the clock is PB. Outputs of these two D-type flip-flop circuits are output signals (EC1 to EC1) of the encoder 30.
The value selected by the multiplexer circuit (MPX) 70 is output (C0 to C9) according to the value of EC6 which is the most significant bit (MSB) of 6). When the MSB is 0, that is, before the pulse PA passes through g31, the counter 1
Is selected, and when the MSB is 1, that is, after the pulse PA has passed g31, the output of the counter 2 is selected. 6 bits of EC1 to 6 are lower data, C0 to
The 10 bits of C9 serve as an input signal of the D-type flip-flop 80 as upper data, the input signal of DCK serves as a clock of the D-type flip-flop 80, and 16-bit data D0 to D15 are output.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG. The operation around the counter, which is a feature of the present embodiment, will be described with reference to FIG. When the input pulse of the PA changes from Low to High, the output signal of g00 in the ring delay pulse generation circuit 10 becomes Hi.
gh to Low, and gates g01 to g6 at the next stage
2 is propagated. In that case, the time required for the propagation of the next stage inverter, it will be delayed by a delay time period with the inverter. Therefore, in order to change the output signal of g62, the signal is propagated with a delay of 62 stages from g00 to g61. Since the number of gates is an odd number of 63 stages and they are connected in a ring shape, they form an oscillating circuit and continue to oscillate as long as the PA input pulse does not return from High to Low. The output of g62 is g
Compared to 31 as shown in the time chart of FIG.
It will be delayed by the delay time of the stage. The output of g31 is input to g311 and input to the pulse generator circuit 40. In the pulse generator circuit, g3
11 and the inverted signal of the signal
Since an EXOR with the signal delayed by a stage is taken, POR in FIG.
The waveform is shown as GCK (point A in FIG. 1). D1 is g3
1 shows the delay time from the change of the output of 1 to the change of PGCK via the three inverters and the EXOR of the pulse generator 40. The point is that the delay element cell 1 used in the circuit 40 is the same as the cell used in the ring delay pulse generation circuit 10. As a result, due to the delay time D1, the falling timing at the point A is surely later than the timing at which the output of g62 changes.

As described above, the two counters 50, 51
Is for counting the number of turns of the ring delay pulse generating circuit 10 by half turning each time. The counter 1 counts up at the rising edge at the point A, and the counter 2 counts up at the rising edge of the inverted signal at the point A, that is, the rising edge at the point B. This count-up value is g
It is considered the same as counting up after passing 62. Here, when the rising signal of PB is input, 63 DFFs d0 to d62 of the pulse selector 20 are set to g.
The state of signal propagation from 00 to g62 is latched. At the transmitted point, the input and output values are the same before and after the gate, and the EXOR output is low only at that point, the EXOR output at the other gates is high, and the EXOR output at the encode 30 is low. 6-bit encoded data indicating the position of. The most significant bit (MSB) EC6 of this data becomes a selection signal for selecting one of the two counter values 50 and 51 at the timing of PB. When EC6 is High, the counter 2 is selected, and when EC6 is Low, the value of the counter 1 is selected. By selecting two counter values in this manner, a signal with a stable counter-up value can be reliably taken out. In FIG. 2, the shaded portion is the count value on the stable side, and since the shaded portion side is reliably selected by the signal of EC6, no mislatch occurs. The number in the shaded portion indicates the number of turns.

As described above, the point is that while the clock for the number of revolutions is taken out from one place, it becomes the same as that counted in two places. As a result, the two counters can be arranged close to each other, the number of wirings can be reduced, and only one pulse generator is required. Further, by using the same delay element cell 1 and making it a counter clock extraction port as shown in FIG.
The fan-out number of 62 is always 2 and has an effect that is useful for making the resolution uniform. Further, each time one latch clock for the PB D-type flip-flop is input, the input signal to the output DFF 80 is determined, thereby facilitating synchronous design to the next and subsequent stages.

FIG. 3 shows a second specific example of the configuration of the present invention. FIG. 4 is a timing chart showing the operation. The difference from FIG. 1 is that the port for taking out the clock of the counter for the number of revolutions is changed from g31 to g62. Therefore, as shown in the operation of FIG.
D-type flip-flop 9
0 and an AND circuit 91 are added. The counter 1 (50) is reset to 0 by the RS signal, and the counter 2 (5) is reset.
1) is set to 1. The D-type flip-flop 90 has a Low output until the circuit goes around once after the input pulse is input to the PA, that is, until the signal is propagated to g62.
Than the value of the forced counter 1 (50) is employed.
With around 1, the output of D-type flip-flop 90, becomes High output, similarly to FIG. 1, the value of the EC 6, one of the counter value either of the two counter values are employed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a pulse phase difference encoding circuit according to a first embodiment.

FIG. 2 is a diagram showing a time chart of the first embodiment.

FIG. 3 is a circuit diagram illustrating a pulse phase difference encoding circuit according to a second embodiment.

FIG. 4 is a diagram showing a time chart of the second embodiment.

[Brief description of reference numerals]

 Reference Signs List 10 ring delay pulse generation circuit 40 pulse generator 50 counter 1 51 counter 2 70 multiplexer

Claims (6)

(57) [Claims] 1. A pulse P input at an arbitrary timing
A with an arbitrary phase difference between A and this pulse PA
The phase difference from the pulse PB to be encoded.
In the pulse phase difference encoding circuit, the final output stage of the plurality of signal delay circuits is delayed by the first signal delay.
And returning the pulse PA to the signal
Do not delay by the delay time of the signal delay circuit in the delay circuit.
A signal delay circuit that has passed this pulse PA
Repeats multiple delayed pulses that are sequentially delayed by the same delay time
And a ring delay pulse generating circuit that generates the delay pulse.
And a plurality of input lines corresponding to the delay pulses
A plurality of output lines, and an input timing of the pulse PB.
The ring delay pattern with a specific time relationship to the
According to the state of the delay pulse from the pulse generating circuit.
A pulse selector for changing the state of the output line, and an output from the output line of the pulse selector.
Corresponding to the state of the output line of the pulse selector.
An encoder for outputting a digital signal, and the delay pulse generated by the ring delay pulse generation circuit.
Two pulse signals inverted from each other based on one of the
And a pulse generator for receiving the pulse signal.
In the ring delay pulse generation circuit, the pulse P
A first counter for counting the number of revolutions of A and an input of the other pulse signal of the pulse generator;
In the ring delay pulse generation circuit, the pulse P
The number of revolutions of A is counted by the count
A second counter that counts out of sync with the first counter, and a first counter that counts the output state of the encoder.
Selecting one of the second counters and selecting the pulse PA
Is the number of revolutions in the ring delay pulse generation circuit.
And a selection circuit for deriving a digital signal representing the digital signal derived by the selection circuit d
It said pulse PA by digital signal output from the encoder
The phase difference sign representing the phase difference between the pulse and the pulse PB
A pulse phase difference encoding circuit characterized in that: 2. The ring delay pulse generation circuit according to claim 2,
The output of each signal delay circuit in the ring delay pulse generator
An input unit connected to the input line and the pulse selector, respectively.
And output units respectively connected to the input lines of
A plurality of second signal delay circuits,
The input unit and the output unit connected to the respective output units of the extension circuit
And a third signal delay circuit having The pulse generator generates the ring delay pulse.
A signal delay circuit having the same configuration as that of the circuit and a second
A signal delay circuit and a third signal delay circuit
And Third signal delay of the ring delay pulse generation circuit
One output of the circuit is connected to said pulse generator
Delay pulse generated from the ring delay pulse generation circuit
Inputting one of the pulses to the pulse generator.
The pulse phase difference encoding circuit according to claim 1, wherein 3. A plurality of signal delay circuits are connected in a ring,
The input first signal is delayed by the plurality of connected signal delays.
Delayed by the delay time of each signal delay circuit in the extension circuit
Signal delay when the first signal has passed
Repeated generation of multiple delayed signals delayed by the circuit delay time
Means for generating a delayed signal, A second signal having a phase difference from the first signal is input;
The plurality of signal delays when the second signal is input
A position for detecting a circulating position of the first signal in the circuit;
Position detecting means, The second signal is input after the first signal is input
The plurality of signal delay circuits before the first signal
Are configured to count the number of orbits
And the first signal is connected in the same loop to the ring.
Before and after passing through one connection point between multiple signal delay circuits
First counting means and second counting means selectively used for switching
Counting means With The second signal selected at the timing when the second signal is input
Count by 1 count means or 2nd count means
The number of turns of the first signal and the position Detection means
And the orbital position of the first signal detected by
And the phase difference between the first signal and the second signal
Pulse phase difference characterized by encoding
Encoding circuit. 4. The delay signal generating means according to claim 1, wherein
An input connected between individual signal delay circuits in the generating means.
It has a force part and an output part connected to the position detecting means.
A plurality of second signal delay circuits; and the second signal delay circuit
Having an input unit and an output unit connected to each output unit of
A third signal delay circuit; A signal delay having the same configuration as that of the delay signal generating means
Extension circuit, second signal delay circuit, and third signal delay circuit
And the delay at the one connection point
The second signal delay circuit of the signal generating means and the third signal delay circuit
Connected via a signal delay circuit, from the one connection point
One of the different signals generated based on the delayed signal generated
To the first counting means and the other signal to the second counting means
Signal means for inputting to each of the means.
4. The pulse phase difference encoding circuit according to claim 3, wherein 5. A plurality of signal delay circuits are connected in a ring.
Then, one pulse PA input at an arbitrary timing is
While circulating in the plurality of connected signal delay circuits.
The number of laps is counted, and the pulse PA
Input timing of pulse PB input with a phase difference of
And determine the orbital position of the pulse PA corresponding to the
The two pulses PA according to the specific position and the count number
And a pulse for encoding the phase difference between the pulse PB and the pulse PB
In the phase difference encoding circuit, Predetermined positions of the plurality of signal delay circuits connected in a ring shape
The pulse PA circulates based on the output signal at
A first counter for counting the number of laps, The output signal at the same position as the predetermined position of the signal delay circuit
The number of revolutions of the pulse PA based on the signal
It is shifted by half a turn from the count timing of one counter.
A second counter to count, The pulse corresponding to the input timing of the pulse PB
The first counter and the second counter are determined by the orbiting position of the PA.
A selection circuit for selecting one of the With The pulse corresponding to the input timing of the pulse PB
PA lap position and the above Said selected by the selection circuit
To the number counted by the first counter or the second counter
Indicates the phase difference between the pulse PA and the pulse PB.
A pulse characterized in that a phase difference sign is obtained.
Phase difference encoding circuit. 6. Each of said signal delay circuits is connected between said signal delay circuits.
A plurality of second signal delay circuits having an input section and an output section
And a respective output of the second signal delay circuit.
And a third signal delay circuit having an input section and an output section.
Delay signal generating means having A signal delay having the same configuration as that of the delay signal generating means
Extension circuit, second signal delay circuit, and third signal delay circuit
And a predetermined position of the signal delay circuit.
The second signal delay circuit of the delay signal generating means;
The signal delay circuit connected through the third signal delay circuit;
Generated based on the output signal at a predetermined position in the extension circuit
One of the different signals is sent to the first counter and the other signal is sent to the first counter.
Signal generating means for inputting to each of two counters; Having
The pulse phase difference encoding circuit according to claim 5, wherein
Road.