SU1481770A1 - Parity signal circuit in shifting binary codes - Google Patents

Abstract

The invention relates to computing and can be used in the organization of the control shifters. The purpose of the invention is to expand the field of application of the device. The device contains a block 1 shift control bits, block 2 bit shifts, node 3 convolution modulo two, switch 4, group 5 modulo adders two. An introduction to the switch 4 device and a group of 5 modulo-adders, which together allow a bit shift, provides control of logical and cyclic codes both right and left for any shift design in block 2 bit shifts and block 1 of check bits, 3 il.

Description

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The invention relates to computing and can be used in organizing the control of binary code shifters.

The purpose of the invention is to expand the field of application of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional block diagram of bit shifts; in fig. 3 - functional diagram of the code-converter unit of bit shifts.

A device for generating a parity signal when shifts binary codes contains block 1 shift check bits, block 2 bit shifts, node 3 convolutions modulo two, switch 4, group 5 modulo adders two, input 6 check bits of the device, inputs 7 and 8 specify byte and bit shifts, respectively, input 9, specify the device shift type, group 10 outputs of the block 2 bit shifts, output 11 of the check bits shift block, output 12 of the device, and discharge 13 indicate the direction of the shift 9 of the device shift type Conditions, group 14 of the control inputs of the switch 4, group 15 of the information inputs of the device, output 16 of the switch 4.

The bit shift block 2 contains a code converter 17, a shifter 18, a decoder 19 of the zero combination, a group of 20 elements AND, bits 21 and 22 of the signs of cyclic shift and direction of the shift 9 of the device type setting shift, output 23 of the code converter 17, output 24 of the decoder 19 the zero combination, the outputs 25 and 26 of the low and high bits of the shifter 18, the output 27 of the first element I of group 20, the group 28 of the outputs of the shifter 18 without the low and high bits, output 29 of the second element And of group 20.

Code Converter 17 contains a group of 30 elements And, elements And 31-33, a group of 34 modulo-two adders.

The check bits shift block 1 shifts the logically or cyclically check bits of the corresponding groups of the K bits (bytes) of the shifted binary code. It can be built on the BIS-shifter type K 1800 BP8.

In block 2 bit shifts, the shifter can also be performed on a BIS shifter of type K 1800 BP8, where logical shifts are provided to the right and left by the amount of bits defined by the code converter 17. This value is an additional code of the number set at input 8 of the task the magnitude of the bit shifts of the device.

At zero shifts at the input 8 of the device, a zero code is set, and a zero signal is generated at the output of the decoder 19 of the zero combination.

During cyclic shifts in the shifter 18 of the 2 bit shifts block, logical shifts are performed to the right or left by (K-1) bits.

Each t-th bit of the information input of the shifter 18 is connected to the (K- - 1-1) -th bit of the output 16 of the switch 4 (CteUK-1).

Switch 4 is -C

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input multiplexer (N is the width of the shifted code). Each entry contains To bits.

The device works as follows.

In the initial state, a group of 15 information inputs of the device is supplied

shifted L-bit code. On

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- the bits of the input 6 control bits of the device are set by the control bits of the bytes of the shifted code.

At the inputs 7 and 8 of setting the value of byte-byte and bit-by-bit device shifts, codes are set that determine how many whole bytes the number of switches 4 shifts and how many bits the selected byte shifts.

At the input 9 of the shift type setting, a code is defined defining the form (logical or cyclic) and the shift direction.

The following types of shift are provided: LL - logical shift to the left, LP - logical shift to the right, CL - cyclic shift to the left, CPU - cylindrical shift to the right. To set the LL, LP, CL, CPU at the input 9, the device shift type assignments in bits 21, 22 (13) are set respectively codes 10, 11, 00, 01. At the output 12 of the device, a predicted parity signal is formed

As an example, a code shift of 1101100010111110 is considered with and. At the input 6 of the control bits of the device, a code 1111 is set. To shift by 10 bits to the inputs 7 and 8, specify the value of the byte-byte and bit-by-bit shifts of the device, the same code 10 must be submitted.

With a logical shift to the left, the shifted code will be equal to 1111100000000000, the parity signal of which is equal to "1.

At the input 9 of the device, this sets the code LL-10. Code 10 is transmitted to the group of control inputs of switch 4, under the action of which code 1011 appears on output 16 of switch 4, which arrives at the information input of shifter 18 as code 1101. At output 11 of block 1 of the control bits of the control bits, code 1100 is generated At the output 23 of the code converter 17, an additional code is generated from code 10, which also

equal to 10. As a result, in the shifter 18, a logical left shift is made by two bits of code 1101 and a shifted code of 0100 is formed on the group 10 of the outputs of the shift block 2. Thus, the codes 0100 and 1100 are generated at the inputs of the convolution node 3 , and at the output 12 of the device - a single signal.

In a similar way, it is carried out in the device to generate the predicted parity signal at logical shifts to the right with installation of the LP-11 code at the input 9 of the device. In this case, the group of control inputs of the switch 4 receives code 01 - the inverted code from the input

7 devices. As a result, at output 16 of switch 4, code 1000 appears, arriving at information input of shifter 18 in the form of code 0001. Next, the device works in the same way as the left shift, with the difference that in block 1 of the control bits and shifter 18 performs a logical right shift.

When a zero code device is installed at the input 8, a zero is formed at the output 24 of the decoder 19 of the zero combination, and the code 11 output 23 of the code converter 17. At the bits of group 28 of the battery 18, a zero code is formed, and at outputs 27, 28 of the And group 30 elements logical zero is formed.

On the whole, the signal at the output 12 of the device is determined by the code at the output of the block 1 for shifting the check bits.

Similarly, when cyclic shifts at the input 9 of the device, a CL or CPU code is set, at which at the input 9 of the device, at bit 21 of the sign of the cyclic shift, there is a zero signal. A code 11 is generated at the output 23 of the code converter 17, and a zero code is output at the outputs of the group 10 of the shift block 2. In shift unit 1, cyclic shifts are performed. The signal at the device output 12 is determined by the code at the output of the shift unit 1.

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Thus, the device provides for the formation of a parity signal when the binary codes are shifted by the shifters of any structure (structure).

Claims (1)

Invention Formula A device for generating a parity signal during binary shifts, containing a check bits shift block, a bit shifts block, a modulo two convolution node, the group of outputs of the bit shifts block connected to the corresponding inputs of the convolution node modulo two, the output of which is a device output the input of the shift value and the input of the shift type of the shift block of the control bits are respectively the input of the job of the value of byte shifts and the input of the task of the type of device shifts, the input of the job The bit shift unit shift value is the input of setting the device bit shifts value, the bit shift block type setting input is connected to the device shift type setting input, the information bits of the control bits shift block is the input of the device control bits, characterized in that In order to expand the field of application of the device, a switch and a group of adders modulo two are entered into it, and the first inputs of modulators are two groups connected to the corresponding input discharges set and device byte shifts, the outputs of the modulators two groups are connected to the switch control inputs of the switch, the output of which is connected to the information input of the blocks of bits shifting, the second inputs of modulators two groups are combined and connected to the bit of the shift type indication of the shift type setting the device, the output of the shift block of the control bits is connected to the input of the modulo two convolution node, the group of information inputs of the switch is a group of information inputs of the device. FI.2  YU