SU1083196A1 - Device for linking processes with storage - Google Patents

Abstract

DEVICE FOR COMMUNICATION PROCESSOR from the storage device comprising kc 1mutator, decoder, encoder, non array register, a register area, wherein the first and second groups of inputs and commutative torus outputs connected respectively to the lane howling and second groups of information inputs and outputs of the device, the inputs of the decoder are connected to the second is a group of information inputs of the device, and the outputs of the decoder are connected to the inputs of the encoder, the first and second groups of outputs of which are connected to the inputs of the Array and Register register, respectively zones whose outputs are connected respectively to the first group of address outputs of the device and to the control inputs of the switch, characterized in that, in order to improve speed, it contains a reversible counter, selector, mode register, element 2И-OR, while the register inputs modes are connected to the second group of information inputs of the device, the first and second outputs of the mode register are connected respectively to the first input of the selector and the first and third inputs of element 2И-OR, the second and fourth inputs of which connected to the first and second control inputs of the device respectively, and the output of element 2И-OR is connected to the second input of the selector, the first and second outputs of which are connected respectively to the summing and reading inputs of the reversible counter, the discharge inputs of which are connected to the second group of information inputs of the device , and the counter outputs are connected to in, a group of address outputs of the device.

Description

The invention relates to computing, in particular, to devices for communication of a processor (microprocessor I and memory), and can be used in building data processing systems based on microcomputers. A device is known that allows the processor and memory to be connected, containing a processor card, at least two memory cards, a memory matrix, connectors, and a Cl3 connection board. The disadvantage of this device is that the memory data format must conform to the process data format The oracle and for the formation of data addresses requires a software modification of the data data address addresses, which reduces the bandwidth of the device. The closest in technical essence to the present invention is a device for communicating a memory and arithmetic device containing a switch, a decoder, an encoder, an array number register, the zone register, the first and second groups of inputs and outputs of the switch are connected respectively to the first and second groups of information inputs and outputs of the device, the inputs of the decoder They are connected to the second group of information inputs of the device, and the outputs of the decoder are connected to the inputs of the encoder, the first and second groups of outputs of which are connected to the inputs of the register of the array number and the zone register, the outputs of which are connected respectively to the first group of address inputs of the device and the control inputs of the switch L2. A disadvantage of the known device is that before each processor accesses the data memory, a programmatic address modification is required (generating and writing a fixed address or an arithmetic operation on the current address. In addition, there is no correspondence between the value of the two-dimensional reference address in the memory and the real the value of spatial reference coordinates creates inconveniences for the programmer when developing digital processing programs for multidimensional signals, for example, image signals. invention - improving device speed. The goal is achieved by the fact that the device contains a switch, a decoder, an encoder, an array number register, a zone register, the first and second groups of inputs and outputs of the switch are connected respectively to the first and second groups of information inputs and outputs the device, the inputs of the decoder are connected to the second group of information inputs of the device, and the outputs of the decoder are connected to the inputs of the encoder, the first and second groups of outputs of which are connected to the inputs of The register of the array number and the zone register, the outputs of which are connected respectively to the first group of address outputs of the device and to the control inputs of the switch, is entered by a reversible counter, selector, mode register, element 2И-OR, and the bit inputs of the mode register are connected to the second group information inputs of the device, the first and second outputs of the mode register are connected respectively to the first input of the selector and the first and third inputs of the element 2И-OR, the second and fourth inputs of which are connected corresponding It is connected with the first and second control inputs of the device, and the output of element 2И-OR is connected to the second input of the selector, the first and second outputs of which are connected respectively to the common and subtractive inputs of the reversible counter, the bit inputs of which are connected to the second group of information inputs of the device , and the outputs of the counter are connected to the second group of address outputs of the device. The drawing shows a block diagram of the proposed device. The device for communication of the processor with the memory device contains the switch 1, the register 2 zones, the register 3 of the array, the decoder 4, the encoder 5, the reversible counter 6, the selector 7, the element 2I-OR 8, the register 9 modes, the processor 10, the memory 11 device , the address bus 12 of the processor, the first 133 and the second 14 groups of the device’s regional outputs, the first 15 and the second 16 groups of information inputs and outputs of the device, 17 and the second 18 control inputs of the device. The device works as follows. The address outputs of the memory device (RAM) 11 are divided into three groups 12, 13 and 14. The first group of 13 address outputs of the device is connected to register 3 of the array, the bit size of which determines the number of arrays contained in the memory. The second group 14 of the address outputs of the device is the outputs of the reversible counter 6 and addresses the information array cells relating to a specific address value. The volume of the subarray is determined by the counter size of the meter and is 2 memory cells formed by the processor. The third group of address inputs of the storage device 11 is connected to the address bus of the processor 10, which addresses memory cells belonging to a specific memory array (n is the width of the processor address bus 10). According to the information bits, the storage device 11 is divided into zones, the selection of which is determined by the state of the register 2 zones. The zone organization of the memory device allows the required zone to be connected to the processor data bus, the width of which corresponds to the processor data bus width. The values of the signals at the outputs of register 2 zones control the operation of switch 1, which connects the first group of 15 inputs and outputs of the memory through the second group of 16 inputs and outputs of the device to the bidirectional data bus of the processor 10. Groups 15 and 16 of the inputs and outputs of the device are the same bidirectional data exchange lines. The switch 1 is made according to the scheme using buffer amplifiers, for example, type 5889IK12, which are included counter to each other. This switch structure allows for the scrambling of the data format of the processor (group of 16 inputs and outputs) with the format of the information inputs and outputs 15 of the storage device. The belonging of the information read from the memory or stored in the memory to the zone or mass is taken into account: when programming the operation of the processor. For a processor, a group of elements 2-5 is an output port, information to which comes from the processor via a bi-directional data bus when it executes the Output (ITD) command. At the same time, the information that determines the array number and the memory zone is recorded in registers 2 and 3 of the zones and arrays, the passage through the decoder 4 and the encoder 5. Thus, the Output command prepares the values of the first group of 13 addresses. device outputs and control signals at the inputs of switch 1 for subsequent calls by processor 10 to memory 11. To change the number of the array or zone, new information is written to registers 2 and 3, i.e. a new output command is executed. The setting of the address of a specific memory location contained in the memory and the modification mode of addresses within this subarray is carried out in the process of writing information to the two-bit register 9 and counter 6, which are the output ports of the processor. The value of the recorded information is taken into account when compiling the program and sent to the port in the process of executing the command Vyv.od. The output state of the first bit of register 9 is given to the direct input of the selector 7 and the operating mode of the reversible counter 6 is determined. If logical 1 is present at the first output of register 9, then the selector 7 transmits a pulse from the curved input to the summing input of counter 6 if the output of register 9 is logic O, the counting pulses are fed to the subtracting input of the counter 6 ". The counting pulses are generated during the execution of the operation of the processor 10 to the memory 11 and are the control signals of the processor 10, For example, Recording and Receiving, which are received from the first 17 and second 18 control inputs of the device to the second and quarter 1 inputs of element 2И-OR 8. The passage of pulses through the element 2 И-OR 8 can be blocked by the corresponding value on the second output of register 9 modes. In the modes of summation or subtraction, the counter modification is arbitrary upon completion of the processor 10 accessing the memory 11, i.e. on the falling edge of the control signals reception and recording. Thus, for the subsequent access of the processor 10 in the memory 11, no programmatic modification of the address is required. In addition, the combination of the summing and subtracting modes of operation of the counter allows the memory address to be quickly changed in the direction of increasing or decreasing. Consider the operation of the device on a specific example using a microprocessor K580IK80. Suppose that memory 11 stores digitized values of a two-dimensional function, for example, images in a picture plane. Each array determined by the value of register 3 of arrays corresponds to one frame of the image in the memory in XY format, where X, Y are spatial coordinates in the rectangular coordinate system. The reference address of the XY image is determined by the value of the bus 12 address of the processor. Each image sample consists of three bytes and corresponds to the numerical values of the three color separations: red R, green Q. and blue B. Let the image point be addressed by the value of a pair of general registers of the NTS processor. A sample of R, G, and B values into registers A, D, and E, as well as their uploading to the memory in the same cells after processing, can be performed using the following processor program: LX1 Н, ХУ - loading of the register pair Н by value of XY; MV1 A - load the battery and output to the register 9. ITD modes and counter 6 information corresponding to the Summation mode, and the zero state of the counter 6}

V A, M - transfer content

Storage unit 11, corresponding to the value of red color separation of 5 liters of R, to register A;

V l, M - transfer of the value of Q to the register D;

V Е, М - transfer of value В 10 to register Е

- commands for processing values of R, Q and B;

V M, A - transfer of the value of R

at . 15

V M, D - transfer of the value of Q to the memory,

MO V M, E - transfer of value B to memory.

This example confirms the advantage of the proposed device in comparison with the known. For six memory accesses, it is not necessary to programmatically modify the address before each address, which eliminates the time spent on its execution. The use of the invention significantly increases the throughput of the device with § §.

The positive effect of the invention is achieved by increasing the capacity of the proposed device by controlling the generation of data memory addresses.

Claims (1)

A DEVICE FOR COMMUNICATING A PROCESSOR WITH A REMEMBERING DEVICE, comprising a switch, a decoder, an encoder, an array number register, a zone register, wherein the first and second groups of inputs and outputs of the switch are connected respectively to the first and second groups of information inputs and outputs of the device, the inputs of the decoder are connected to the second group information inputs of the device, and the outputs of the decoder are connected to the inputs of the encoder, the first and second groups of outputs of which are connected to the inputs of the register of the array number and register, respectively eons, the outputs of which are connected respectively to the first group of address outputs of the device and the control inputs of the switch, characterized in that, in order to improve performance, it contains a reversible counter, selector, mode register ,. 2-OR-element, with the bit inputs + inputs of the mode register connected to the second group of information inputs of the device, the first and second outputs of the mode register are connected respectively to the first input of the selector and the first and third inputs of the 2-OR element, the second and fourth inputs of which are connected respectively with the first and second control inputs of the device, and the output of the 2-OR element is connected to the second input of the selector,. the first and second outputs of which are connected, respectively, with the summing and subtracting inputs of the reversible counter, the bit inputs of which are connected to the second group of information inputs of the device, and the outputs of the counter are connected to the second group of address outputs of the device. With