SU1042190A1 - Digital asynchronous pulse signal regenerator - Google Patents

Abstract

DIGITAL ASYNCHRONOUS REGENE-NEPA-TOR PULSE SIGNALS, containing the pulse generator, the first and second elements AND, the outputs of which are connected respectively to the summing and subtracting inputs of the reversible counter, as well as the output trigger and the input inverter. the output of which is connected to the first input of the second element I, and the input combined with the first input of the first element I, characterized in that, in order to improve noise immunity by changing the integration time of pulses and pauses, a variable divider frequency divider and a decoder are introduced the output of which is connected to the installation input of the unit of the output trigger, and with the second input of the first element I, and the second output with the output setting of the zero output trigger and with the second input of the second element I, third inputs of first and second AND gates connected to the (L nepBbiM and second outputs of the frequency divider with a variable division ratio, whose input is connected to the output of the pulse generator 4 U:. about O

Description

The invention relates to a signal transmission technique and can be used in devices for receiving pulsed signals with an unknown time of their arrival, operating under conditions of strong impulse noise. A digital integrator regenerator is known, containing a generator & tor, elements AND, counters, an output trigger and a control unit in which the integration of pulses and pauses is performed by the same counter G. However, in a known regenerator, the polarity of the input signal affects the zero setting input. Therefore, if there are crushing or spurious pulses in the input signal, the distance between them is smaller than the filling time of the chip, a false reset occurs, and the counter does not record the corresponding pulse or pause of the input signal. The closest to the invention is a digital asynchronous regenerator of pulsed signals, containing a pulse generator, the first and second elements AND, the KOTOjaax outputs are connected respectively to the summing and subtracting inputs of the reversible counter, as well as the output 1 three; the house of the second element is And, and the input is united with the first input of the first element And 2. However, this regenerator has low noise immunity. The purpose of the invention is to improve the robustness by changing the integration time of pulses and pauses. .. The goal is achieved by the fact that a digital asynchronous pulse signal regenerator containing a pulse generator, the first and second elements are AND, whose audio outputs are connected respectively to the summing and calculating inputs of a reversible counter, as well as the output trigger and the input inverter, the output of which is connected to the first the input of the second element is And, and the input is combined with the first input of the first element And, a frequency divider with a variable division factor and a decoder are entered, the first output of which is connected to the input of the output unit The second trigger is with the second input of the first element I, and the second output with the input of the zero output trigger setting, and with the second input of the second element I, while the third inputs of the first and second elements I are connected with the first and second outputs de-. variable frequency division factor whose input is connected to the output of the pulse generator. FIG. 1 shows the structural electrical circuit of the proposed regenerator; in fig. 2 - stress diagrams for his work. Digital asynchronous pulse signal regenerator contains 1 pulse generator, 2 frequency divider with variable division factor, first and second, elements OF and 4, reversible counter 5, decoder 6, output trigger 7 and input inverter 8. The regenerator works as follows. The pulses of the generator 1 are fed to the input of the splitter outputs of which pulses are formed, the ratio of the frequencies of which corresponds to the statistical characteristics of the duration of distortions of pulses and pauses. below the frequency of the pulses arriving at the second input of the second element and 4. When the signal of a logical unit (Fig. 2a and 2S) arrives at the device input, the pulses from the first the output of the divider 2 is fed to the summing input of the reversing counting | chika 5 (Fig, 26). If the number of pulses is sufficient to fill the recalculated counter (Fig. 2), the decoder 6 generates a fill signal at the first output (Fig. 2e), which sets the output trigger 7 to one state (Fig. 2j3, and through the first element And 3 prohibits the arrival of pulses of the divider 2 to the summing input of the reversible counter 5. The input signal of the logical zero (FIG, 2 l and 2 6) passed through the input inverter 8, allows the arrival of pulses from the second output of the divider 2 through the second element I 4 (Fig. 2d ) on the counting input of the reversible counter ka 5. When the reversal counter reaches zero, the decoder 6 generates a signal at the second output, which prevents the pulses from passing through the second element 4 (Fig. 2g), and simultaneously sets the output trigger 7 to the zero state. and the az is carried out by feeding counting pulses to different reversing inputs.

Hord counter. Pozprmu, unlike the prototype, the opportunity. set arbitrary grade-. the solution is between the time constants of the integration of the pulses and pauses of the sig- nal ,, which increases the noise immunity | But under conditions, when the crushing time and spurious impulses have iI I 1

Ullllll

varying statistical characteristics.

In addition, the proposed regenerator has a simpler circuit than the prototype, since it uses a simpler output type: a trigger, and there is no modulo two.

i

i

111 IN II tin

Lll

Jl

L

imiH II

Jul

Claims (1)

DIGITAL ASYNCHRON REG - PULSE SIGNAL NERATOR, containing a pulse generator, the first and second elements And, the outputs of which are connected respectively to the summing and subtracting inputs of the reversible counter, as well as the output trigger and input inverter, the output of which is connected to the first input of the second element And, and combined with the first input of the first AND element, characterized in that, in order to increase noise immunity by changing the integration time of pulses and pauses, a frequency divider with a variable coefficient is introduced into it by a division factor and a decoder, the first output of which is connected to the installation input of the output trigger unit, and with the second input of the first element And, and the second output - with the output of the zero setting of the output trigger and with the second input of the second And element, while the third inputs of the first and second elements And connected to the first and second outputs of the frequency divider with a variable division ratio, the input of which is connected to the output of the pulse generator. "SU 1042190> signals and can be used in devices for receiving signals with an unknown of their arrival, operating in strong pulse