SU1429345A1 - Correlation signal receiver - Google Patents

Abstract

The invention relates to the field of telecommunications, in particular to detection receivers. The purpose of the invention is to improve the noise immunity. The device contains a generator 1, multipliers 2, 3, integrators 4, 5, quadratic detectors 10, 11 adder 12, a decoder 13. The device has a frequency divider 6, keys 7, 8, element 9 and the counter 14, the integrators 4 and 5 are discharged through the keys 7 and 8 from the pulses coming from the frequency divider 6. The pulse frequency determines the integration period, and the pulses are generated by the frequency divider 6 from the oscillator reference signal. When the decoder 13 triggers falsely on both inputs of the And 9 element, the same potential appears, which changes the state of its output connected to the reset input of the counter 14. This resets the counter 14 and shows that there is no input signal. 1 Fig. X

Description

The invention relates to electro-communication, in particular, to a signal detection receiver.

The purpose of the invention is higher noise immunity.

The drawing shows a correlation signal receiver circuit.

The correlation signal receiver contains the generator 1, the first 2 and

ten

/ W1th 3 multipliers, first 4 and 5 square integrators, divisor 6 - often | first 7 and second 8 keys, And 9, first 10 and second P quadratic detectors, adder 12, 15 decoder 13 and counter N.

The correlation signal receiver works as follows.

; The reference signal from generator 1 after-T ifnaeT to the first inputs of the first 2 and 20 Bi 6poro 3 multipliers, the second of which receives input signals. The result of multiplying the accumulation on the first 4 and second 5 integrators. Since the integration time cannot be infinite to decide, the first 4 and second 5 integrators are discharged through the first 7 and second 8 keys from the pulses coming from frequency dividers 6, the pulse frequency determines the integrand period, the pulses themselves and the formulas divider 6. -frequencies from the supports-. nbto signal generator o35

and to the input of the counter 14 receives a false pulse.

To eliminate this phenomenon, pulses from the output of the decoder are simultaneously applied to one of the inputs of the element 9, to the second input of which in antiphase pulses are output from the output of the frequency divider 6. When the signal is received, these pulses are equal in duration and are synchronous in time of arrival, therefore the output state of the AND 9 element does not change, which permits the counter to be counted 14 °

When the decoder 13 triggers on both inputs of the AND 9 element, the same potential appears, which changes the state of its output connected to the reset input of the counter 14. This resets the counter reading, which indicates the absence of an input signal.

Claims (1)

Invention Formula 25 thirty To obtain the result of addition, independent of the sign of the input signal, the result of integration is squared by the first 10 and second 11 quadratic detectors and added 4 by the adder 12. To the output of the adder 12, the decoder 13 is attached, which, when the signal exceeds the specified threshold level, on the counting input of the counter 14, pulse. This sets the bandwidth I of the receiver. The counter 14 is reset when the required number of pulses arrives, which increases the reliability of reception, however, when a pulsed disturbance arrives, under real conditions it has a short duration but high amplitude, which exceeds the threshold level, the decoder 13 works Vgap-up Order 5146/57 A correlation signal receiver containing a first multiplier connected in series, a first integrator, a first quadratic detector and a second multiplier connected in series, a second integrator, a second quadratic detector, and a generator, adder, decoder, the input of which is connected to the adder output, to the first and second the inputs of which are connected to the outputs of the first and second quadratic detectors, respectively, the output of the generator is connected to the first inputs of the first and second multipliers 40, respectively, whose second inputs are combined, characterized in that, in order to improve noise immunity, a frequency divider, first and second keys, and an AND element are introduced. 45 and the counter, with the first input the counter is connected to the decoder code and the first input of the And element, the second input of the counter is connected to the output of the And element, the second input of which 50 is connected to the output of the frequency divider and the inputs of the first and second keys, the output of the first key is connected to the output of the first integrator, and the output of the second key is connected to the output 55 of the second integrator, while the generator output is connected to the input of the frequency divider. Circulation 660 Subscription 0 five 0 5 and to the input of the counter 14 receives a false pulse. To eliminate this phenomenon, pulses from the output of the decoder are simultaneously applied to one of the inputs of the element 9, to the second input of which in antiphase pulses are output from the output of the frequency divider 6. When the signal is received, these pulses are equal in duration and are synchronous in time of arrival, therefore the output state of the AND 9 element does not change, which permits the counter to be counted 14 ° When the decoder 13 triggers on both inputs of the AND 9 element, the same potential appears, which changes the state of its output connected to the reset input of the counter 14. This resets the counter reading, which indicates the absence of an input signal. Invention Formula