SU1015443A1 - Buffer memory - Google Patents

Abstract

BUFFER STORAGE DEVICE, contains registers, NOT elements, AND group of elements, OR group of elements. They are distinguished by the fact that, in order to increase the reliability of devices, a counter, an annular shift register, triggers, a delay element, elements AND and OR, and an additional AND group of elements are entered into It, and one of the information inputs of the same-name triggers of each register are connected between are the information inputs of the device, others with the outputs of the NOT elements whose inputs are the information inputs of the device, the single outputs of each register trigger connected to the first inputs of the elements And groups, st The triggering inputs of the triggers of each register are combined and connected to the second inputs of the elements of the AND groups and the outputs of the elements AND of an additional group: one of the inputs of which is connected to the corresponding outputs of the ring shift register j of the outputs of the elements of the AND groups are connected to the inputs of the elements OR information output device, the first input of the first element. that OR, the first information input of the first trigger and the first input of the first AND element are combined and. are the first synchronization input of the device, the output of the first element AND is connected to the first input of the second element OR and the counting input of the account-; The key and is the output of the device transmission transfer, the second input of the second element OR, the installation input of the first trigger and one of the inputs of the second element AND are combined and are the second clock; the input of the device, another input of the second element I is connected to the output of the ring shift register, the output of the second element I is connected to the first information input of the second trigger and the first input three. the second OR element, the output of which is connected to the gate. input of the second trigger, the counter output is connected to the second information inputs of the first and second triggers, the input of the delay element and the second inputs of the first and third elements OR, and the output of the Device inhibit, the output of the delay element is connected to the installation the input of the annular shift register, the output of the first element OR is connected with the gate input of the first trigger, the output of the second element OR with the secondary EHE inputs of the elements AND an additional circuit uppa, the counting input of the ring shifted register and the first input of the third element AND whose output is the control output of the device, the single output of the second trigger is connected to the second input of the third element And and the third inputs of the elements of the AND groups, the single output of the first trigger is connected to the second input the first element And the installation input of the counter.

Description

The invention relates to computing technology and mocking to be used in the construction of information storage devices in a discrete technology. A buffer storage device is known that holds the registers of the L1 numbers, the bits of which of the same name are connected by a successor, but through the AND element, which controls the two-stroke shift register, in each row of which the main and auxiliary triggers are connected through the elements And, the zero output of each the main trigger register of the shift, except the first one, is connected to the AND element of the previous bit of this register, and the output of the AND element of each bit of the control shift register is connected to the zero input of the auxiliary trigger of the same bit, a single input of the auxiliary trigger of the subsequent bit and inputs of the corresponding elements AND registers of the storage of numbers Cl. The disadvantage of this device is that it does not track the moment when the last received information word was output from the device, then if there are signals on the read bus, the output at the device output is false, zero. In addition, the device has a complex rewrite control scheme, which requires a multi-cycle rewrite control system. Known memory device containing registers, fired on the triggers, information inputs. each of which is connected to the outputs of the elements of the record: and, the write bus, as well as the elements OR and NOT, the output of each of which is connected to the first input of each even record element, and the input of each element is NOT connected To the first input of each odd record element, the second inputs of the recording elements are connected to the recording bus, the inputs of each element OR are connected respectively to the information inputs of each trigger, and the output of each element OR is connected to the gating input of each trigger C2. A disadvantage of the known device is the possibility of information distortions, due to the fact that the device does not ensure continuous operation in the data transfer mode, since it does not monitor the time when all receiving registers are filled. Therefore, in the case of receiving information from the device until all the receiving registers are completely filled, a false, zero (output, information is output at the device output. And in the case of a delay in receiving information from the device, after filling all receiving registers, the true values of the transmitted information may be lost. words. moreover, the device does not detect the moment of the information word received from the device of the last device received by the device, - 4iO also leads to a distortion of the information output by the device. The attacks reduce the reliability of the device. The purpose of the invention is to increase the reliability of the device. This goal is achieved in that a buffer memory device containing registers, elements NOT, groups of elements AND, a group of elements. OR, a counter, an annular shift register, triggers, a delay element are entered. AND and OR elements and an additional AND group of elements, one of the information inputs of the same trigger of each register are interconnected and are information inputs of the device, others with element outputs These NOT inputs whose inputs are device information inputs, the unit outputs of each register trigger are connected to the first inputs of elements AND groups, the gate inputs of the triggers of each register are combined and connected to the second inputs of elements AND groups and the outputs of elements AND an additional group, one of the inputs of which connected to the corresponding outputs of the ring shift register; the outputs of the elements AND groups are connected to the inputs of the elements OR of the group whose outputs are information outputs of the device, ne The first input of the first element OR, the first information input of the first trigger and the first input of the first element AND are the first synchronization input of the device, the output of the first AND element is connected to the input of the second OR element and the counter input of the counter. the second element OR, the installation input of the first trigger and one of the inputs of the second element AND are combined and are the second synchronization input of the device, the other & the stroke of the second AND element is connected to the output to The fender shift register, the output of the second element AND is connected to the first information input of the second trigger and the primary input of the third element. ORI whose output is connected to the gate input of the second trigger, the output of the counter Is connected to the second OOM and information inputs. Dami first and second triggers,

the input of the delay element and the second inputs of the first and third OR elements is the output of the Device lock, the output of the lock element is connected to the installation input of the ring shift register, the output of the first OR element is connected to test input of the first trigger, the output of the second OR element with the second inputs of AND elements additional group, the counting input of the ring shift register and the first input of the third element And, the output of which is the control output of the device, the unit output of the second trigger connected to the second input of the third element And the third inputs of the elements of the AND groups, the single output of the first trigger is connected to the second input of the first element AND and the installation input of the counter.

The drawing shows a functional diagram of the proposed device.

The buffer memory contains registers I - l, executed on the 2–2 triggers, groups 3–3 of the I 4–4 elements, block 5 of the inverters, made on the HE elements 6–6, ringed, shifted. 7., counter S, additional group 9 elements AND 10 10, group 11 elements OR 12 12, elements AND 13-15, elements OR 16-18, triggers 19 and 20, delay element 21, information inputs 22, first and the second synchronization inputs 23 and 24, information outputs 25, output 26 Disable transmission of the device, output 27 Disable the device, as well as control input 28.

The device works as follows

Before starting operation, the device is reset, as a result of which all triggers 2 - 2 in each register l - l, counter 8 and triggers 19 and 20 are in the initial, zero position, the first bit of the register 7 is written 1. After that, the device is ready for operation,

Then, the first information word enters the information inputs 22 of the device, followed by the SI sync pulse, acting on the second sync input. 24. This information word comes in the direct code to informational inputs J, and in the reverse code to informational inputs K triggers 2–2 in each register 1–1. However, only the first register is prepared for receiving information. as the first bit of register 7 is in the unit state. Therefore, the signal arriving from the first output of register 7 prepares the first element AND 10 for operation. Consequently, the sync pulse SI1 enters through the second element OR 17 “the first element AND 10 to the gate inputs GP bqex of the 2–2 flip-flops of the first one. register 1. On the guard front of this sync pulse information, nakho-. On the information inputs J - and K of all the flip-flops 2 - 2 of the first register, l, is written in the first. register 1, and register 7 rewrites 1 from the first bit to the second, preparing the second element AND 10 for operation.

On the leading edge of the first clock pulse SI1, which enters the input R of the first flip-flop -19, the zero state of the first flip-flop 19 is confirmed. This completes the recording of the first information word in the first register 1.

Then, at the first synchronization input 23, a sync pulse SI2, shifted relative to the sync pulse SI, arriving at the second synchronization input 24, is received for a half follow period. The clock pulse SI2 is fed to the information input J and through the first element OR 16 to the gate input Cp of the first trigger 19, which, on the falling edge of this pulse, switches to the one state, preparing the first element for operation. And 13 and counter 8.

After that, the information input 22 of the device receives the second information word, followed by the synchro impulse SI1; step on the second synchro-; The input is 24. This information word in the forward code arrives at the information “Liv-return code moves to the information inputs K of flip-flops 2 - 2 of each register, 1. However, only the second register 2 is ready for receiving information, so. as the second register bit 7 is in a single state, which is prepared by the second AND 10 element for operation.

On the leading edge of the second sync pulse SI1, which enters the input R of the first flip-flop 19, the first flip-flop 19 switches to the zero state, prohibiting the operation of the first element 13 and counter 8. On the trailing edge of the second sync pulse SI1 entering the second element, OR 17 and the second element And 10 on the building inputs Cp of all the flip-flops 2 - 2 of the second register 1, the second information word is written in the second register 1, and the register 7 rewrites 1 of the second bit V, the third bit, preparing for operation the third element AND 10. On by this

The write to the second information word in the second reception register 1 ends.

Then, the first sync pulse SI2 is fed through the first clock input 23, shifted relative to the sync pulse SI1 by a half-half: the following code. The sync pulse CH2 on the trailing edge switches to the unit sos, then the first trigger 19, preparing the first element And 13 and the counter 8 for operation.

Then, the third information word enters through the information inputs 22 of the device, followed by the synchrometer CI1 arriving at the second synchronization input 24. According to the previously described cycle, it is recorded in the third register 1,

Further, the process of recording information words of register 1 is analogous to the previously described one.

After recording the (n-l) -ro information word in (n-1), and register 1, the nth digit of register 7 is in the unit state, preparing for operation the nth element 10, the second element 14, and elements 4.

Then, the information word enters the information inputs 22 of the device, followed by the synchronization pulse SI1, on the falling edge of which it is written in the nth register 1, the register 7 rewrites 1 from the nth bit to the first, and the second trigger 20 through the second element I 14 switches in a single state, preparing for operation the third element I 15.

After that, the information inputs 22 of the device act next to the next information word, accompanied by a sync pulse.

On the leading edge with: SI1 inlays at the outputs of elements I 4 - 4 of the first group Z, the first stored in the first register: page 1, information word, KOTCipoe goes to the first inputs of the elements OR 12 - 12, then to the information outputs 25 of the device. This information word is accompanied by a sync pulse arriving: from the output of the third element I 15 to the control output 28 of the device.

On the falling edge of the clock S1, the information word on the information inputs 2.2 of the device is written to the first register l, and the register 7 performs the census 1 of the first bit of the second.

60

From this point on, the device operates in the mode of receiving and transferring information.

The following information word arrives at the information inputs.

22 devices accompanied by SI1 sync pulse. .I

On the leading edge of the clock SI1 at the outputs of elements AND 4 of group 3, a second information word appears, stored in the second register 1, which goes to the second inputs of the elements OR 1212 of group 11 and to the information outputs 25 of the device. This informational word is accompanied by a sync pulse at the control input 28 of the device.

On the trailing edge of the sync pulse Cc1, CI1 records the information word located at the information inputs 22 of the device into the second register 1, and register 7 performs the census 1 from the second bit into the third.

The process of recording and issuing regular information words arriving at information inputs 22 of the device and stored in registers 1 -1 is similar to that described earlier.

during the operation of the device in the mode of receiving and transmitting information, the register 7 may repeatedly return to the initial state. It depends on the number of transmitted information words in the device.

The mode of reception and transmission of information continues as long as the condition of following the clock pulses CI1 and CI2 is met, which requires a strictly defined sequence CI1 and CI2 one after another, shifted relative to each other by a half-follow period.

In the case of stopping the transmission of information to the device at the second synchronization input 24, there is no regular clock SI1-, which would have returned the first trigger 19 to the zero state, prohibiting the operation of the first And element 13. Therefore, upon the arrival of the next sync pulse SI2 at the output of the first terminal I 13, prepared by .- (to work by the previous sync pulse CI2, the pulse CI2 appears, which noCTynaet to the input of the second element OR 17 and from the output ocy-S there is output from the next, receiving register 1 - 1 information word on the outputs 25 of the device, followed by exit sync 2.8 Arrangements and writes into register l -1 zero signal information on the previously described cycle.

The pulse from the first element And 13 also goes to the counting input of the counter 8, whose capacity is equal to the number of registers, and to the output 26 Prohibition of transmission, prohibiting further; arrival of sync pulses CHl at the second synchronization input 24 and stopping the transmission of information words to the device. From this point on, the mode of only issuing information words by the device begins. Upon receipt of the next sync pulse, the SI 2 is carried out according to the previously described cycle, issuing from the next register the information on the device outputs 25, followed by the clock signal on the device output 28. The process of issuing the next information words stored in registers 1 - 1 is similar to that previously described. The process of issuing the next information words, stored 11 | ihs in registers I - 1, continues until counter 8 is completely filled, which corresponds to the output of the last information word stored in the device. Upon the overflow of the counter 8, an impulse appears at its output, on the falling edge of which the first 19 and second 20 triggers switch to the zero state, stopping the output of information words from the device, and at output 27 The impulse preventing the arrival of SI synchro pulses at the first the synchronization input 23. The signal from the output of the counter 8 through the delay element 21, delayed by its duration, also goes to the setup input of the register 7, has recorded 1 for the first bit. At this, the device stops . Thus, the proposed buffer storage device has an increased reliability of the information output during continuous operation of the device in the mode of receiving information preexisting, since it prevents the output of false information at the output of the device at the time of issuance from the device, as well as at the time of transfer of the last stored information word by the device.

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Claims (1)

BUFFER MEMORY DEVICE containing registers, NOT elements, AND element groups, OR element group. about t and h e e ^? with the fact that, in order to increase the reliability of & devices, a counter, an annular shift register, triggers, a delay element, AND and OR elements, and an additional group of AND elements are introduced into It, and one of the information inputs of the same triggers of each register are interconnected and are information inputs of the device, others with outputs of elements NOT, the inputs of which are information inputs of the device, the unit outputs of each trigger of registers are connected to the first inputs of elements AND groups, gating inputs three the headers of each register are combined and connected, with the second inputs of the elements AND groups, and the outputs of the elements AND of the additional group, one of the inputs of which are connected to the corresponding outputs of the circular shift register / outputs of the elements and groups are connected to the inputs of the elements OR groups, the outputs of which are information outputs devices, the first input of the first OR element, the first information input of the first trigger and the first input of the first AND element are combined and are the first synchronizing input of the device, the output is not The first AND element is connected to the first input of the second OR element and the counting input of the counter: is the output Lock for transmitting the device, the second input of the second OR element, the installation input of the first trigger and one of the inputs of the second AND element are combined and are the second clock : device input, OTHER input of the second ^: element AND is connected to the output of the annular shift register, the output of the second element And is connected to the first information input of the second trigger and the first input of the three. of the third OR element, the output of which is connected to the strobe input of the second trigger, the counter output is connected to the second information inputs of the first and second triggers, the input of the delay element and the second inputs of the first and third elements OR and is the output Device inhibit, the output of the element 'delay ^ is connected to the installation input ring ·) of the target shift register, the output of the first OR element is connected · to the gate input of the first trigger, the output of the second OR element with the second inputs of elements AND of an additional group, with the input of the annular shift register and the first input of the third element,, the output of which is the control output of the device, the single output of the second trigger is connected to the second input of the third element And the third inputs of the elements And groups, the single output of the first trigger is connected to the second input of the first element And and installation input of the counter.