SU1012291A1 - Graphic data reading device - Google Patents

Description

The invention relates to automation and computer technology, in particular to devices for converting and inputting graphic information of complex shapes into a computer, and can be used as an external input device for a main set of a universal computer, as well as in various specialized computer aided design systems.

A device for reading graphic information is known, which contains a tablet with two mutually orthogonal groups of coordinate buses, a coarse count counter, outputs via switches connected to the inputs. tablet axes, precision counter, coordinate remover, inductively connected to axes and through an amplifier connected to one input of a null organ, a control unit whose input is connected to a null organ output, and outputs - with switches, with counters coarse and heavy samples, and a unit for the formation of reference read pulses, current inputs associated with the outputs of the coordinate tires of the tablet, and a control input with a counter of the exact count, and the output of the specified block is connected to another input house zero-organ 1}.

The disadvantage of the device lies in its structural complexity.

Closest to the invention is a device comprising a plate made in the form of two systems of mutually perpendicular coordinate buses, inductively connected to the coordinate buses, a coordinate remover connected to the amplification unit of the crossbar switch connected to a pulse distributor connected to a generator clock pulses, memory blocks, counter, AND, OR elements and delay elements.

The disadvantage of this device lies in the low accuracy of the device.

The purpose of the invention is to eliminate this drawback, i.e. increase the accuracy of the device.

The goal is achieved by the fact that a device containing a tablet made in the form of two systems of mutually orthogonal coordinate buses connected to the corresponding switches of the group, a gain unit,

The INPUT of which is connected to the coordinate remover, and the output is connected to the OR element, to the first memory block and AND element, the first counter connected to the OR element output and to the first decoder connected to another input of the first AND element whose output is connected to the element OR, pulse distributor, the inputs of which are connected to the pulse generator and the first decoder, and the outputs are connected to the switches of the group, to the second, third and fourth sweepers, to the first and second delay elements and to one input of analog digital digits A converter whose other input is connected to the first memory block, and the outputs are connected to the input of the OR element and to the same inputs of the AND elements of the first group, the other inputs of which are connected to the second delay element connected to the third, the delay element, the inverter connected to the unit gain, second and third memory blocks and elements of the second group, the second decoder is connected to the third counter and to the inputs of the amplifier; the first switch connected to the second memory block and to the second decoder, the second element NT And, the inputs of which are connected to the first delay element and the inverter, and the output is connected to the first switch, the third decoder connected to the Fourth counter, the second switch connected to the third memory block, to the second delay element and to the third decoder, the compare unit whose inputs are connected to the second switch, to the third delay element and to the AND elements of the first group, and the output is connected to the OR element and to the AND elements of the second group, the fourth delay element connected to the comparison unit and from the element and 1 (1 of the second group and the first adder, the inputs of which are connected to the first switch and to the outputs of AND gates of the second group, and the output is the output device.

In this case, the gain unit contains the second adder, the inputs of which are co-. the amplifiers are dinene, the output is the output of the block, and the keys whose inputs are the inputs of the block, and the outputs are connected to the inputs of the corresponding amplifiers. The drawing shows a block diagram of the device. The device contains a tablet 1 with coordinate tires, a puller 2 coordinate dimat, a group of switches 3 and, a distributor of 5 pulses, the first 6 second 7 and third 8 decoders, the first 9, the second 10, the third Pi fourth and 12 counters, the first 13 and the second It AND elements, analogue-digital gig recorder 15 element 16 OR, 17 pulse generator, first 18 and second 19 groups of elements AND, first 20, second 21, third 22 and fourth 23 delay elements, first 2k, second 25 and third 26 TI, first 27 and second 28 switches, first adder 29, comparison unit 30, inverter 31 and a gain unit 32 comprising keys 33, amplifiers 3, and {second adder 35. The device operates as follows. After installing the sighting crossover puller 2 at the readable point, the operator launches a survey of the X tire of the tablet 1 with the Start signal. With this signal, which enters the input of the element 16 OR, the counter 9 is set to state 1. The first output of the decoder 6 thus appears potential. allowing the pulse generator 17 to pass to the first output of the distributor 5, from which they come to the input of switch 3 and the input of counter 10 of coarse tires X. Switch 3 performs alternate switching and excitation of buses X, and counter 10 counts the number of excited buses . 8, since the counter 11 is in the initial state O, at the first output of the decoder 7 there is a resolving potential, opening the corresponding key 33, connecting the corresponding amplifier 3 to the puller 2. This amplifier has the highest gain factor and its chuv. Capacity determines the size of the step of laying the tires. As soon as the bus interrogates the nearest 2 coordinate to the puller, the output of the amplifier k is reached by a signal arriving at the adder 35. The signal from the output of the concave 35 through element 16 OR switches the counter 9 to the state corresponding to the second operation, during which re-excitation of the last polled bus, as well as alternately connecting amplifiers, 33. If, when connecting the first amplifier, the output of the adder 35 does not receive a signal, then the output of the inverter 31 will be a high level, through the element Ir and depending on the code of the decoder 7 (depending on which amplifier is connected) selects from the block 25 a code corresponding to the length of the corresponding zone. This happens until a signal is output at the output of the adder 35, which switches the counter 9 to the next state. In this case, a third operation is performed, during which the amplitude of the received signal is converted into a code. The converted signal through b / ak 2 is fed to the analog input of analog-digital converter 15, the digital input of which receives pulses from the third output of distributor 5. At the end of the conversion cycle, the signal from the pulse output of analog-digital converter 15 switches the count-. The pin 9 is in the state corresponding to the execution of the fourth operation, during which the formation of the exact reference code. For this, the distributor 5 at the fourth output generates a series of pulses that arrive at the counter 12 connected to the decoder 8. Depending on the code at the output of the decoder 8, the switch 28 selects from the cells of the delay element J2 sequentially selected there the digital codes of the amplitudes of the induced signals and transmits them to the input of block 30, to the second input of which, synchronously with this, the digital value of the amplitude of the converted signal arrives, taken through elements 19 AND of the group with the information output of analog-digital converter 15. When the codes are equal, the strobe pulse from the output of the delay element 22 is fed to the output of the block 30 and then to the input of the counter 9, thereby stopping the arrival of pulses to the input of the block 30. At the same time, through the delay 23 the signal is transferred intermediate code

5 10122916

the total number of coordinates on the totalizer of the counters 10 and the adder

29. In combination with the contents of Sum-29. .

matora it gives the complete code of the exact introduction of new nodes and blocks, and

reference coordinates than end-to-new constructive connections

The formation of a complete coordinate code 5 makes it possible to significantly increase the points that make up the content of the proposed device.

Claims (2)

1. DEVICE FOR READING GRAPHIC INFORMATION, containing a tablet, made in the form of two systems of mutually orthogonal coordinate buses connected to the corresponding. group switches, the amplification unit, the input of which is connected to the coordinate stripper, the e-output is connected to the OR element, to the first memory block and the And element, the first counter connected to the output of the OR element and to the first decoder connected to another input of the first And element, the output of which is connected to an OR element, a pulse distributor, the inputs of which are connected to a pulse generator. and with the first decoder, and the outputs are connected to the switches of the group, to the second, third and fourth counters, to the first and second delay elements and to one input of the analog-to-digital converter, the other input of which is connected to memory unit, and the outputs are connected to the input of the OR element and to one of the inputs of the elements AND of the first group, the other inputs of which are connected to the second delay element connected to the third delay element, the inverter connected to the amplification unit, the second and third memory blocks and elements And the second group, which entails the fact that, in order to increase the accuracy of the device, it contains a second * decoder connected to the third counter and to the inputs of the amplification unit, the first switch connected to the second memory unit and to the second decoder, WTO oh element · And, the inputs of which are connected to the first delay element and to the inverter, and the output is connected to the first switch, the third decoder connected to the fourth counter, the second switch g connected to the third memory block, to the second delay element and to the third a decoder, a comparison unit, the inputs of which are connected to the second switch, to the third delay element and to the AND elements of the first group, and the output is connected to the OR element and to the AND elements of the second group, the fourth delay element connected to the comparison unit and to ementami And the second group and the first adder, the inputs of which are connected to the first switch and to the outputs of AND gates of the second group, and the output is an output device. 2. The device according to p. ^ Characterized in that the amplification unit contains a second adder, the inputs of which are connected to the amplifiers, and the output is the output of the unit, and the keys, the inputs of which are the inputs of the unit, and the outputs are connected to the inputs of the respective amplifiers. SU „, .1012291