SG85630A1 - Executing partial-width packed data instructions - Google Patents

Executing partial-width packed data instructions

Info

Publication number
SG85630A1
SG85630A1 SG9901386A SG1999001386A SG85630A1 SG 85630 A1 SG85630 A1 SG 85630A1 SG 9901386 A SG9901386 A SG 9901386A SG 1999001386 A SG1999001386 A SG 1999001386A SG 85630 A1 SG85630 A1 SG 85630A1
Authority
SG
Singapore
Prior art keywords
packed data
data instructions
executing partial
width packed
width
Prior art date
Application number
SG9901386A
Other languages
English (en)
Inventor
Roussel Patrice
Thakkar Ticky
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG85630A1 publication Critical patent/SG85630A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
SG9901386A 1998-03-31 1999-03-19 Executing partial-width packed data instructions SG85630A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/053,127 US6230253B1 (en) 1998-03-31 1998-03-31 Executing partial-width packed data instructions

Publications (1)

Publication Number Publication Date
SG85630A1 true SG85630A1 (en) 2002-01-15

Family

ID=21982113

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9901386A SG85630A1 (en) 1998-03-31 1999-03-19 Executing partial-width packed data instructions

Country Status (7)

Country Link
US (3) US6230253B1 (zh)
CN (3) CN100367269C (zh)
DE (1) DE19914617C2 (zh)
GB (1) GB2339040C (zh)
HK (1) HK1027402A1 (zh)
SG (1) SG85630A1 (zh)
TW (1) TW470914B (zh)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US6230257B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6192467B1 (en) 1998-03-31 2001-02-20 Intel Corporation Executing partial-width packed data instructions
US6230253B1 (en) 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US7395302B2 (en) * 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US6233671B1 (en) 1998-03-31 2001-05-15 Intel Corporation Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
US6418529B1 (en) 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US6687806B1 (en) * 2000-06-15 2004-02-03 Advanced Micro Devices, Inc. Apparatus and method for generating 64 bit displacement and immediate values
CN1299198C (zh) * 2001-06-27 2007-02-07 凌阳科技股份有限公司 由可改变的指令格式而提高程序码密集度的微控制器结构
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
US7200738B2 (en) * 2002-04-18 2007-04-03 Micron Technology, Inc. Reducing data hazards in pipelined processors to provide high processor utilization
DE10225230B4 (de) * 2002-06-06 2004-10-21 Infineon Technologies Ag Prozessor und Verfahren zum gleichzeitigen Ausführen einer Berechnung und eines Kopiervorgangs
US7426529B2 (en) * 2002-06-06 2008-09-16 Infineon Technologies Ag Processor and method for a simultaneous execution of a calculation and a copying process
US7249350B2 (en) * 2002-09-30 2007-07-24 Intel Corporation Optimized translation of scalar type SIMD instructions into non-scalar SIMD instructions
US7987341B2 (en) 2002-10-31 2011-07-26 Lockheed Martin Corporation Computing machine using software objects for transferring data that includes no destination information
US7668897B2 (en) * 2003-06-16 2010-02-23 Arm Limited Result partitioning within SIMD data processing systems
US7237096B1 (en) * 2004-04-05 2007-06-26 Sun Microsystems, Inc. Storing results of producer instructions to facilitate consumer instruction dependency tracking
US7383427B2 (en) * 2004-04-22 2008-06-03 Sony Computer Entertainment Inc. Multi-scalar extension for SIMD instruction set processors
US20050251649A1 (en) * 2004-04-23 2005-11-10 Sony Computer Entertainment Inc. Methods and apparatus for address map optimization on a multi-scalar extension
US7389406B2 (en) * 2004-09-28 2008-06-17 Intel Corporation Apparatus and methods for utilization of splittable execution units of a processor
US20060085781A1 (en) 2004-10-01 2006-04-20 Lockheed Martin Corporation Library for computer-based tool and related system and method
US7257695B2 (en) * 2004-12-28 2007-08-14 Intel Corporation Register file regions for a processing system
CN100452090C (zh) * 2006-03-14 2009-01-14 腾讯科技（深圳）有限公司 一种实现高动态光照范围的方法及系统
US7761694B2 (en) * 2006-06-30 2010-07-20 Intel Corporation Execution unit for performing shuffle and other operations
US7783862B2 (en) * 2006-08-07 2010-08-24 International Characters, Inc. Method and apparatus for an inductive doubling architecture
US20080071851A1 (en) * 2006-09-20 2008-03-20 Ronen Zohar Instruction and logic for performing a dot-product operation
US8631224B2 (en) * 2007-09-13 2014-01-14 Freescale Semiconductor, Inc. SIMD dot product operations with overlapped operands
US8103858B2 (en) * 2008-06-30 2012-01-24 Intel Corporation Efficient parallel floating point exception handling in a processor
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
US8335912B2 (en) * 2009-04-22 2012-12-18 Oracle America, Inc. Logical map table for detecting dependency conditions between instructions having varying width operand values
US20100274961A1 (en) * 2009-04-22 2010-10-28 Golla Robert T Physically-indexed logical map table
US8458444B2 (en) * 2009-04-22 2013-06-04 Oracle America, Inc. Apparatus and method for handling dependency conditions between floating-point instructions
US8504805B2 (en) * 2009-04-22 2013-08-06 Oracle America, Inc. Processor operating mode for mitigating dependency conditions between instructions having different operand sizes
US8495125B2 (en) * 2009-05-27 2013-07-23 Microchip Technology Incorporated DSP engine with implicit mixed sign operands
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
US9052890B2 (en) * 2010-09-25 2015-06-09 Intel Corporation Execute at commit state update instructions, apparatus, methods, and systems
US8914615B2 (en) 2011-12-02 2014-12-16 Arm Limited Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format
WO2013095580A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
US10866807B2 (en) 2011-12-22 2020-12-15 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride
US10223111B2 (en) 2011-12-22 2019-03-05 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
WO2013095554A1 (en) 2011-12-22 2013-06-27 Intel Corporation Processors, methods, systems, and instructions to generate sequences of consecutive integers in numerical order
US9336000B2 (en) 2011-12-23 2016-05-10 Intel Corporation Instruction execution unit that broadcasts data values at different levels of granularity
WO2013095618A1 (en) 2011-12-23 2013-06-27 Intel Corporation Instruction execution that broadcasts and masks data values at different levels of granularity
US9513912B2 (en) 2012-07-27 2016-12-06 Micron Technology, Inc. Memory controllers
US20140281418A1 (en) * 2013-03-14 2014-09-18 Shihjong J. Kuo Multiple Data Element-To-Multiple Data Element Comparison Processors, Methods, Systems, and Instructions
US9477467B2 (en) * 2013-03-30 2016-10-25 Intel Corporation Processors, methods, and systems to implement partial register accesses with masked full register accesses
US10228941B2 (en) * 2013-06-28 2019-03-12 Intel Corporation Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US9424034B2 (en) * 2013-06-28 2016-08-23 Intel Corporation Multiple register memory access instructions, processors, methods, and systems
US9495155B2 (en) 2013-08-06 2016-11-15 Intel Corporation Methods, apparatus, instructions and logic to provide population count functionality for genome sequencing and alignment
US9513907B2 (en) 2013-08-06 2016-12-06 Intel Corporation Methods, apparatus, instructions and logic to provide vector population count functionality
US9355061B2 (en) 2014-01-28 2016-05-31 Arm Limited Data processing apparatus and method for performing scan operations
US10108454B2 (en) * 2014-03-21 2018-10-23 Intel Corporation Managing dynamic capacitance using code scheduling
JP6307975B2 (ja) * 2014-03-28 2018-04-11 富士通株式会社 演算処理装置及び演算処理装置の制御方法
FR3021428B1 (fr) 2014-05-23 2017-10-13 Kalray Multiplication de matrices de bits utilisant des registres explicites
TWI681300B (zh) * 2014-11-14 2020-01-01 美商凱為有限責任公司 在64位元資料路徑上實行128位元simd操作之方法、系統及電腦可讀取媒體
US10001995B2 (en) * 2015-06-02 2018-06-19 Intel Corporation Packed data alignment plus compute instructions, processors, methods, and systems
US10459731B2 (en) * 2015-07-20 2019-10-29 Qualcomm Incorporated Sliding window operation
US20170192789A1 (en) * 2015-12-30 2017-07-06 Rama Kishnan V. Malladi Systems, Methods, and Apparatuses for Improving Vector Throughput
US10901940B2 (en) 2016-04-02 2021-01-26 Intel Corporation Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
US10296342B2 (en) * 2016-07-02 2019-05-21 Intel Corporation Systems, apparatuses, and methods for cumulative summation
US10838720B2 (en) * 2016-09-23 2020-11-17 Intel Corporation Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectors
CN113190791A (zh) 2018-08-06 2021-07-30 华为技术有限公司 矩阵的处理方法、装置及逻辑电路
CN111459546B (zh) * 2020-03-30 2023-04-18 芯来智融半导体科技(上海)有限公司 一种实现操作数位宽可变的装置及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3636106A1 (de) * 1985-10-23 1987-04-23 Mitsubishi Electric Corp Digitaler signalprozessor
WO1997023821A1 (en) * 1995-12-26 1997-07-03 Intel Corporation A system for signal processing using multiply-add operations
US5701508A (en) * 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675001A (en) 1970-12-10 1972-07-04 Ibm Fast adder for multi-number additions
US3723715A (en) 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions
FR2212952A5 (zh) * 1972-12-29 1974-07-26 Cit Alcatel
US3900724A (en) * 1974-02-11 1975-08-19 Trw Inc Asynchronous binary multiplier using non-threshold logic
JPS5824941A (ja) * 1981-08-07 1983-02-15 Hitachi Ltd 演算装置
JPS58182754A (ja) * 1982-04-19 1983-10-25 Hitachi Ltd 演算処理装置
JPS60134974A (ja) * 1983-12-23 1985-07-18 Hitachi Ltd ベクトル処理装置
US4945479A (en) * 1985-07-31 1990-07-31 Unisys Corporation Tightly coupled scientific processing system
JPS6284335A (ja) * 1985-10-09 1987-04-17 Hitachi Ltd 乗算回路
US5021945A (en) 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US4890218A (en) 1986-07-02 1989-12-26 Raytheon Company Variable length instruction decoding apparatus having cross coupled first and second microengines
US4985848A (en) * 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
US5047975A (en) * 1987-11-16 1991-09-10 Intel Corporation Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode
US5189636A (en) * 1987-11-16 1993-02-23 Intel Corporation Dual mode combining circuitry
US5126964A (en) * 1988-04-01 1992-06-30 Digital Equipment Corporation High performance bit-sliced multiplier circuit
US4972362A (en) * 1988-06-17 1990-11-20 Bipolar Integrated Technology, Inc. Method and apparatus for implementing binary multiplication using booth type multiplication
CA1311063C (en) * 1988-12-16 1992-12-01 Tokumichi Murakami Digital signal processor
US5134693A (en) * 1989-01-18 1992-07-28 Intel Corporation System for handling occurrence of exceptions during execution of microinstructions while running floating point and non-floating point instructions in parallel
US5081698A (en) * 1989-02-14 1992-01-14 Intel Corporation Method and apparatus for graphics display data manipulation
US5001662A (en) * 1989-04-28 1991-03-19 Apple Computer, Inc. Method and apparatus for multi-gauge computation
US5590365A (en) * 1990-03-30 1996-12-31 Kabushiki Kaisha Toshiba Pipeline information processing circuit for floating point operations
JP2651267B2 (ja) * 1990-07-26 1997-09-10 富士通株式会社 演算処理装置及び演算処理方法
DE69131840T2 (de) * 1990-09-18 2000-04-20 Fujitsu Ltd Verfahren zur Vervielfältigung eines geteilten Speichers
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5303355A (en) 1991-03-27 1994-04-12 Motorola, Inc. Pipelined data processor which conditionally executes a predetermined looping instruction in hardware
US5241493A (en) 1991-12-16 1993-08-31 International Business Machines Corporation Floating point arithmetic unit with size efficient pipelined multiply-add architecture
US5311508A (en) 1991-12-23 1994-05-10 Square D Company Apparatus for receiving and decoding a serial data packet containing the status of a network of single point I/O devices
US5210711A (en) 1992-02-26 1993-05-11 Sony Corporation Of America Very fast variable input multi-bit adder
US5606677A (en) 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
JPH06242928A (ja) 1993-02-22 1994-09-02 Nec Corp 加算器およびこれを用いた乗算回路
US5327369A (en) * 1993-03-31 1994-07-05 Intel Corporation Digital adder and method for adding 64-bit, 16-bit and 8-bit words
US5806049A (en) 1993-04-21 1998-09-08 Petruzzi; Christopher R. Data processing system for global assessment of investment opportunity and cost
US5390135A (en) * 1993-11-29 1995-02-14 Hewlett-Packard Parallel shift and add circuit and method
US5883824A (en) * 1993-11-29 1999-03-16 Hewlett-Packard Company Parallel adding and averaging circuit and method
US5673427A (en) 1994-03-01 1997-09-30 Intel Corporation Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
US5642306A (en) * 1994-07-27 1997-06-24 Intel Corporation Method and apparatus for a single instruction multiple data early-out zero-skip multiplier
US5579253A (en) * 1994-09-02 1996-11-26 Lee; Ruby B. Computer multiply instruction with a subresult selection option
US5819101A (en) * 1994-12-02 1998-10-06 Intel Corporation Method for packing a plurality of packed data elements in response to a pack instruction
BR9509845A (pt) * 1994-12-02 1997-12-30 Intel Corp Microprocessador com operação de compactação de elementos de operação compósitos
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US6006318A (en) * 1995-08-16 1999-12-21 Microunity Systems Engineering, Inc. General purpose, dynamic partitioning, programmable media processor
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
EP0847551B1 (en) 1995-08-31 2012-12-05 Intel Corporation A set of instructions for operating on packed data
US5721892A (en) 1995-08-31 1998-02-24 Intel Corporation Method and apparatus for performing multiply-subtract operations on packed data
US5936872A (en) 1995-09-05 1999-08-10 Intel Corporation Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations
US6470370B2 (en) * 1995-09-05 2002-10-22 Intel Corporation Method and apparatus for multiplying and accumulating complex numbers in a digital filter
US5852726A (en) 1995-12-19 1998-12-22 Intel Corporation Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
US5835748A (en) 1995-12-19 1998-11-10 Intel Corporation Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file
WO1997024681A1 (en) 1995-12-19 1997-07-10 Intel Corporation A computer system performing a two-dimensional rotation of packed data representing multimedia information
US5793661A (en) 1995-12-26 1998-08-11 Intel Corporation Method and apparatus for performing multiply and accumulate operations on packed data
US5835392A (en) 1995-12-28 1998-11-10 Intel Corporation Method for performing complex fast fourier transforms (FFT's)
US5880983A (en) 1996-03-25 1999-03-09 International Business Machines Corporation Floating point split multiply/add system which has infinite precision
US6041403A (en) 1996-09-27 2000-03-21 Intel Corporation Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
US6061521A (en) * 1996-12-02 2000-05-09 Compaq Computer Corp. Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle
TW357318B (en) * 1997-03-18 1999-05-01 Ind Tech Res Inst Branching forecast and reading device for unspecified command length extra-purity pipeline processor
US5884071A (en) * 1997-03-31 1999-03-16 Intel Corporation Method and apparatus for decoding enhancement instructions using alias encodings
FR2766353B1 (fr) 1997-07-28 1999-11-26 Dimso Sa Implant, notamment plaque anterieure cervicale
US6260137B1 (en) * 1997-09-12 2001-07-10 Siemens Aktiengesellschaft Data processing unit with digital signal processing capabilities
US5864703A (en) * 1997-10-09 1999-01-26 Mips Technologies, Inc. Method for providing extended precision in SIMD vector arithmetic operations
US7197625B1 (en) * 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6178482B1 (en) 1997-11-03 2001-01-23 Brecis Communications Virtual register sets
US6192467B1 (en) 1998-03-31 2001-02-20 Intel Corporation Executing partial-width packed data instructions
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US6122725A (en) 1998-03-31 2000-09-19 Intel Corporation Executing partial-width packed data instructions
US6233671B1 (en) 1998-03-31 2001-05-15 Intel Corporation Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
US6230257B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6378060B1 (en) * 1998-08-24 2002-04-23 Microunity Systems Engineering, Inc. System to implement a cross-bar switch of a broadband processor
US6272512B1 (en) 1998-10-12 2001-08-07 Intel Corporation Data manipulation instruction for enhancing value and efficiency of complex arithmetic
US7313788B2 (en) * 2003-10-29 2007-12-25 International Business Machines Corporation Vectorization in a SIMdD DSP architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3636106A1 (de) * 1985-10-23 1987-04-23 Mitsubishi Electric Corp Digitaler signalprozessor
US5701508A (en) * 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
WO1997023821A1 (en) * 1995-12-26 1997-07-03 Intel Corporation A system for signal processing using multiply-add operations

Also Published As

Publication number Publication date
US7467286B2 (en) 2008-12-16
US6970994B2 (en) 2005-11-29
GB2339040A (en) 2000-01-12
CN1286002C (zh) 2006-11-22
US20020010847A1 (en) 2002-01-24
US6230253B1 (en) 2001-05-08
CN1244675A (zh) 2000-02-16
GB9907221D0 (en) 1999-05-26
CN1595389A (zh) 2005-03-16
GB2339040C (en) 2008-06-16
GB2339040B (en) 2000-07-12
CN1595390A (zh) 2005-03-16
TW470914B (en) 2002-01-01
CN100385432C (zh) 2008-04-30
DE19914617C2 (de) 2002-10-31
HK1027402A1 (en) 2001-01-12
CN100367269C (zh) 2008-02-06
US20050216706A1 (en) 2005-09-29
DE19914617A1 (de) 1999-10-14

Similar Documents

Publication Publication Date Title
GB2339040C (en) Executing partial-width packed data instructions
GB0023549D0 (en) Executing partial-width packed data instructions
PL346295A1 (en) Holographic decorated tube package
IL139028A0 (en) Greenhouse
HU9900892D0 (en) Enclosed multiple-biofilter
GB9927369D0 (en) Packaging
EP1126980A4 (en) BOOKLET
GB9810694D0 (en) Spooler
GB9801050D0 (en) Packaging
GB9802837D0 (en) Package
GB2335135B (en) Headgear
GB9812428D0 (en) Packaging
GB9821504D0 (en) Brimstone
GB2353784B (en) Reel
CA83282S (en) Reel
PL108960U1 (en) Package
PL107710U3 (en) Package
AU137456S (en) Package
AU138196S (en) Package
GB9802491D0 (en) Package
GB9828450D0 (en) Packaging
GB9806693D0 (en) Packaging
GB9820625D0 (en) Packaging
GB9924303D0 (en) Packaging
GB9806243D0 (en) Packaging