SG70142A1 - Providing dual work function doping - Google Patents

Providing dual work function doping

Info

Publication number
SG70142A1
SG70142A1 SG1998005847A SG1998005847A SG70142A1 SG 70142 A1 SG70142 A1 SG 70142A1 SG 1998005847 A SG1998005847 A SG 1998005847A SG 1998005847 A SG1998005847 A SG 1998005847A SG 70142 A1 SG70142 A1 SG 70142A1
Authority
SG
Singapore
Prior art keywords
work function
providing dual
dual work
function doping
doping
Prior art date
Application number
SG1998005847A
Other languages
English (en)
Inventor
Gary Bela Bronner
Jeffrey Peter Gambino
Jack Allan Mandelman
Carl J Radens
William Robert Patrick Tonti
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG70142A1 publication Critical patent/SG70142A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
SG1998005847A 1998-01-06 1998-12-16 Providing dual work function doping SG70142A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/003,106 US5937289A (en) 1998-01-06 1998-01-06 Providing dual work function doping

Publications (1)

Publication Number Publication Date
SG70142A1 true SG70142A1 (en) 2000-01-25

Family

ID=21704186

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1998005847A SG70142A1 (en) 1998-01-06 1998-12-16 Providing dual work function doping

Country Status (7)

Country Link
US (1) US5937289A (ja)
EP (1) EP0929101A1 (ja)
JP (1) JP3184806B2 (ja)
KR (1) KR100303410B1 (ja)
CN (1) CN1113402C (ja)
SG (1) SG70142A1 (ja)
TW (1) TW464956B (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274467B1 (en) * 1999-06-04 2001-08-14 International Business Machines Corporation Dual work function gate conductors with self-aligned insulating cap
US6281064B1 (en) * 1999-06-04 2001-08-28 International Business Machines Corporation Method for providing dual work function doping and protective insulating cap
KR100482745B1 (ko) * 2000-12-29 2005-04-14 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조 방법
AU2002362489A1 (en) 2001-09-28 2003-04-14 Schott Glas Method and device for shaping a structured body and body produced according to said method
US6709926B2 (en) * 2002-05-31 2004-03-23 International Business Machines Corporation High performance logic and high density embedded dram with borderless contact and antispacer
US7256083B1 (en) * 2002-06-28 2007-08-14 Cypress Semiconductor Corporation Nitride layer on a gate stack
US8080453B1 (en) 2002-06-28 2011-12-20 Cypress Semiconductor Corporation Gate stack having nitride layer
US7371637B2 (en) * 2003-09-26 2008-05-13 Cypress Semiconductor Corporation Oxide-nitride stack gate dielectric
US8252640B1 (en) 2006-11-02 2012-08-28 Kapre Ravindra M Polycrystalline silicon activation RTA
EP2559200A4 (en) 2010-04-12 2015-04-22 Qualcomm Inc DETECTION OF LIMITS OF COMMUNICATIONS WITH LOW OVERHEAD ON A NETWORK
US20150333188A1 (en) 2014-05-15 2015-11-19 Spansion Llc Tilted implant for poly resistors

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4201603A (en) * 1978-12-04 1980-05-06 Rca Corporation Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4745079A (en) * 1987-03-30 1988-05-17 Motorola, Inc. Method for fabricating MOS transistors having gates with different work functions
US4786611A (en) * 1987-10-19 1988-11-22 Motorola, Inc. Adjusting threshold voltages by diffusion through refractory metal silicides
US5028564A (en) * 1989-04-27 1991-07-02 Chang Chen Chi P Edge doping processes for mesa structures in SOS and SOI devices
JP2823393B2 (ja) * 1991-09-09 1998-11-11 シャープ株式会社 半導体メモリ素子及びその製造方法
US5241202A (en) * 1992-03-12 1993-08-31 Micron Technology, Inc. Cell structure for a programmable read only memory device
JPH06151828A (ja) * 1992-10-30 1994-05-31 Toshiba Corp 半導体装置及びその製造方法
US5378641A (en) * 1993-02-22 1995-01-03 Micron Semiconductor, Inc. Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant
US5500379A (en) * 1993-06-25 1996-03-19 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device
US5308780A (en) * 1993-07-22 1994-05-03 United Microelectronics Corporation Surface counter-doped N-LDD for high hot carrier reliability
US5614432A (en) * 1994-04-23 1997-03-25 Nec Corporation Method for manufacturing LDD type MIS device
JPH0878698A (ja) * 1994-09-06 1996-03-22 Sony Corp 半導体装置の製造方法
US5576579A (en) * 1995-01-12 1996-11-19 International Business Machines Corporation Tasin oxygen diffusion barrier in multilayer structures
US5605861A (en) * 1995-05-05 1997-02-25 Texas Instruments Incorporated Thin polysilicon doping by diffusion from a doped silicon dioxide film
DE19612950C1 (de) * 1996-04-01 1997-07-31 Siemens Ag Schaltungsstruktur mit mindestens einem MOS-Transistor und Verfahren zu deren Herstellung
US5770490A (en) * 1996-08-29 1998-06-23 International Business Machines Corporation Method for producing dual work function CMOS device

Also Published As

Publication number Publication date
CN1223464A (zh) 1999-07-21
KR19990067774A (ko) 1999-08-25
CN1113402C (zh) 2003-07-02
TW464956B (en) 2001-11-21
US5937289A (en) 1999-08-10
KR100303410B1 (ko) 2001-09-26
JPH11260935A (ja) 1999-09-24
JP3184806B2 (ja) 2001-07-09
EP0929101A1 (en) 1999-07-14

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