SG63746A1 - Method and system for testing memory - Google Patents
Method and system for testing memoryInfo
- Publication number
- SG63746A1 SG63746A1 SG1997003428A SG1997003428A SG63746A1 SG 63746 A1 SG63746 A1 SG 63746A1 SG 1997003428 A SG1997003428 A SG 1997003428A SG 1997003428 A SG1997003428 A SG 1997003428A SG 63746 A1 SG63746 A1 SG 63746A1
- Authority
- SG
- Singapore
- Prior art keywords
- testing memory
- testing
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40123—Interconnection of computers and peripherals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2697196P | 1996-09-20 | 1996-09-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG63746A1 true SG63746A1 (en) | 1999-03-30 |
Family
ID=21834899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1997003428A SG63746A1 (en) | 1996-09-20 | 1997-09-16 | Method and system for testing memory |
Country Status (7)
Country | Link |
---|---|
US (1) | US5815509A (fr) |
EP (1) | EP0831496B1 (fr) |
JP (1) | JPH10133965A (fr) |
KR (1) | KR19980024806A (fr) |
DE (1) | DE69717385T2 (fr) |
SG (1) | SG63746A1 (fr) |
TW (1) | TW365003B (fr) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6141767A (en) * | 1998-04-03 | 2000-10-31 | Sony Corporation | Method of and apparatus for verifying reliability of contents within the configuration ROM of IEEE 1394-1995 devices |
US6182179B1 (en) * | 1998-04-20 | 2001-01-30 | National Instruments Corporation | System that is able to read and write using a transmission medium and is able to read stored information via a model information structure using a different transmission medium |
US6094530A (en) * | 1998-04-29 | 2000-07-25 | Intel Corporation | Remotely monitoring execution of a program |
GB2338791B (en) * | 1998-06-22 | 2002-09-18 | Advanced Risc Mach Ltd | Apparatus and method for testing master logic units within a data processing apparatus |
US6247151B1 (en) | 1998-06-30 | 2001-06-12 | Intel Corporation | Method and apparatus for verifying that data stored in a memory has not been corrupted |
KR100295444B1 (ko) * | 1998-09-21 | 2001-07-12 | 윤종용 | 원격억세스서버의모뎀가입자정합장치 |
JP3606133B2 (ja) * | 1999-10-15 | 2005-01-05 | セイコーエプソン株式会社 | データ転送制御装置及び電子機器 |
US6704820B1 (en) * | 2000-02-18 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Unified cache port consolidation |
US6757763B1 (en) * | 2000-04-07 | 2004-06-29 | Infineon Technologies North America Corpration | Universal serial bus interfacing using FIFO buffers |
US6643728B1 (en) | 2000-05-30 | 2003-11-04 | Lexmark International, Inc. | Method and apparatus for converting IEEE 1284 signals to or from IEEE 1394 signals |
US20030204796A1 (en) * | 2002-04-24 | 2003-10-30 | Wen-Hsi Lin | Serial input/output testing method |
US7428678B1 (en) * | 2004-09-22 | 2008-09-23 | Cypress Semiconductor Corporation | Scan testing of integrated circuits with high-speed serial interface |
US8176406B2 (en) * | 2008-03-19 | 2012-05-08 | International Business Machines Corporation | Hard error detection |
JP5309938B2 (ja) * | 2008-12-05 | 2013-10-09 | 富士通株式会社 | 要求処理装置、要求処理システムおよびアクセス試験方法 |
US10489241B2 (en) * | 2015-12-30 | 2019-11-26 | Arteris, Inc. | Control and address redundancy in storage buffer |
KR102533377B1 (ko) * | 2018-04-13 | 2023-05-18 | 삼성전자주식회사 | 로드 생성기를 포함하는 메모리 장치 및 그것을 동작시키는 방법 |
CN113126913A (zh) * | 2021-03-26 | 2021-07-16 | 井芯微电子技术(天津)有限公司 | 一种基于并行ram的数据阵列管理方法、装置和存储设备 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4788683A (en) * | 1986-01-14 | 1988-11-29 | Ibm Corporation | Data processing system emulation with microprocessor in place |
US5167020A (en) * | 1989-05-25 | 1992-11-24 | The Boeing Company | Serial data transmitter with dual buffers operating separately and having scan and self test modes |
US5428806A (en) * | 1993-01-22 | 1995-06-27 | Pocrass; Alan L. | Computer networking system including central chassis with processor and input/output modules, remote transceivers, and communication links between the transceivers and input/output modules |
-
1997
- 1997-09-16 SG SG1997003428A patent/SG63746A1/en unknown
- 1997-09-19 EP EP97116367A patent/EP0831496B1/fr not_active Expired - Lifetime
- 1997-09-19 DE DE69717385T patent/DE69717385T2/de not_active Expired - Lifetime
- 1997-09-19 US US08/934,156 patent/US5815509A/en not_active Expired - Lifetime
- 1997-09-20 KR KR1019970047916A patent/KR19980024806A/ko not_active Application Discontinuation
- 1997-09-22 JP JP9257187A patent/JPH10133965A/ja active Pending
- 1997-09-27 TW TW086113723A patent/TW365003B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR19980024806A (ko) | 1998-07-06 |
JPH10133965A (ja) | 1998-05-22 |
DE69717385D1 (de) | 2003-01-09 |
TW365003B (en) | 1999-07-21 |
DE69717385T2 (de) | 2003-06-12 |
EP0831496A3 (fr) | 1999-06-02 |
EP0831496B1 (fr) | 2002-11-27 |
US5815509A (en) | 1998-09-29 |
EP0831496A2 (fr) | 1998-03-25 |
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