SG49816A1 - Non-disruptive randomly addressable memory system - Google Patents

Non-disruptive randomly addressable memory system

Info

Publication number
SG49816A1
SG49816A1 SG1996006749A SG1996006749A SG49816A1 SG 49816 A1 SG49816 A1 SG 49816A1 SG 1996006749 A SG1996006749 A SG 1996006749A SG 1996006749 A SG1996006749 A SG 1996006749A SG 49816 A1 SG49816 A1 SG 49816A1
Authority
SG
Singapore
Prior art keywords
array
reprogramming
storage elements
configuration
disruption
Prior art date
Application number
SG1996006749A
Other languages
English (en)
Inventor
Rafael C Camarota
Original Assignee
Rafael C Camarota
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rafael C Camarota filed Critical Rafael C Camarota
Publication of SG49816A1 publication Critical patent/SG49816A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories

Landscapes

  • Mathematical Physics (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Storing Facsimile Image Data (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
SG1996006749A 1992-07-02 1993-07-01 Non-disruptive randomly addressable memory system SG49816A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US90770992A 1992-07-02 1992-07-02

Publications (1)

Publication Number Publication Date
SG49816A1 true SG49816A1 (en) 1998-06-15

Family

ID=25424523

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996006749A SG49816A1 (en) 1992-07-02 1993-07-01 Non-disruptive randomly addressable memory system

Country Status (8)

Country Link
US (2) US5488582A (ko)
EP (2) EP0877385B1 (ko)
JP (1) JPH07509800A (ko)
KR (1) KR100320605B1 (ko)
AT (2) ATE184728T1 (ko)
DE (2) DE69326467T2 (ko)
SG (1) SG49816A1 (ko)
WO (1) WO1994001867A1 (ko)

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US5821772A (en) * 1996-08-07 1998-10-13 Xilinx, Inc. Programmable address decoder for programmable logic device
US5838165A (en) * 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5946219A (en) * 1996-10-30 1999-08-31 Atmel Corporation Method and system for configuring an array of logic devices
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US6046603A (en) * 1997-12-12 2000-04-04 Xilinx, Inc. Method and apparatus for controlling the partial reconfiguration of a field programmable gate array
US6028445A (en) * 1997-12-30 2000-02-22 Xilinx, Inc. Decoder structure and method for FPGA configuration
US6172520B1 (en) 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
JPH11355961A (ja) * 1998-06-05 1999-12-24 Yazaki Corp Ｐｔｃ素子を有する回路保護装置及びｐｔｃ素子を有する回路保護装置を備えた電気接続箱
US6097210A (en) * 1998-08-04 2000-08-01 Xilinx, Inc. Multiplexer array with shifted input traces
US6069489A (en) 1998-08-04 2000-05-30 Xilinx, Inc. FPGA having fast configuration memory data readback
US6137307A (en) * 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
US6305005B1 (en) 1999-01-14 2001-10-16 Xilinx, Inc. Methods to securely configure an FPGA using encrypted macros
US6301695B1 (en) 1999-01-14 2001-10-09 Xilinx, Inc. Methods to securely configure an FPGA using macro markers
US6324676B1 (en) 1999-01-14 2001-11-27 Xilinx, Inc. FPGA customizable to accept selected macros
US6160418A (en) * 1999-01-14 2000-12-12 Xilinx, Inc. Integrated circuit with selectively disabled logic blocks
US6357037B1 (en) 1999-01-14 2002-03-12 Xilinx, Inc. Methods to securely configure an FPGA to accept selected macros
US6654889B1 (en) 1999-02-19 2003-11-25 Xilinx, Inc. Method and apparatus for protecting proprietary configuration data for programmable logic devices
US6191614B1 (en) 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6262596B1 (en) 1999-04-05 2001-07-17 Xilinx, Inc. Configuration bus interface circuit for FPGAS
US6255848B1 (en) 1999-04-05 2001-07-03 Xilinx, Inc. Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA
JP2000311943A (ja) 1999-04-27 2000-11-07 Mitsubishi Electric Corp 半導体装置
DE10081643D2 (de) 1999-06-10 2002-05-29 Pact Inf Tech Gmbh Sequenz-Partitionierung auf Zellstrukturen
US6204687B1 (en) 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US7069320B1 (en) 1999-10-04 2006-06-27 International Business Machines Corporation Reconfiguring a network by utilizing a predetermined length quiescent state
US7269738B1 (en) 1999-12-16 2007-09-11 Nokia Corporation High throughput and flexible device to secure data communication
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US7162644B1 (en) 2002-03-29 2007-01-09 Xilinx, Inc. Methods and circuits for protecting proprietary configuration data for programmable logic devices
US6996713B1 (en) 2002-03-29 2006-02-07 Xilinx, Inc. Method and apparatus for protecting proprietary decryption keys for programmable logic devices
EP1363132B1 (en) * 2002-05-13 2007-09-05 STMicroelectronics Pvt. Ltd A method and device for testing of configuration memory cells in programmable logic devices (PLDS)
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
KR100597788B1 (ko) * 2004-12-17 2006-07-06 삼성전자주식회사 프로그램 동작 속도를 개선하는 불휘발성 반도체 메모리장치의 페이지 버퍼와 이에 대한 구동방법
US9231595B2 (en) * 2013-06-12 2016-01-05 International Business Machines Corporation Filtering event log entries
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Also Published As

Publication number Publication date
JPH07509800A (ja) 1995-10-26
DE69330974T2 (de) 2002-05-29
EP0877385B1 (en) 2001-10-17
DE69326467D1 (de) 1999-10-21
EP0877385A3 (en) 1999-03-03
ATE207234T1 (de) 2001-11-15
US5488582A (en) 1996-01-30
EP0650631A4 (en) 1995-12-13
ATE184728T1 (de) 1999-10-15
WO1994001867A1 (en) 1994-01-20
EP0877385A2 (en) 1998-11-11
KR950702736A (ko) 1995-07-29
KR100320605B1 (ko) 2002-04-22
EP0650631A1 (en) 1995-05-03
DE69326467T2 (de) 2000-05-31
US5805503A (en) 1998-09-08
DE69330974D1 (de) 2001-11-22
EP0650631B1 (en) 1999-09-15

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