SG43762A1 - Digital processor and viterbi decoder having shared memory - Google Patents

Digital processor and viterbi decoder having shared memory

Info

Publication number
SG43762A1
SG43762A1 SG1996000664A SG1996000664A SG43762A1 SG 43762 A1 SG43762 A1 SG 43762A1 SG 1996000664 A SG1996000664 A SG 1996000664A SG 1996000664 A SG1996000664 A SG 1996000664A SG 43762 A1 SG43762 A1 SG 43762A1
Authority
SG
Singapore
Prior art keywords
shared memory
digital processor
viterbi decoder
viterbi
decoder
Prior art date
Application number
SG1996000664A
Other languages
English (en)
Inventor
Homayoon Sam
Marc Stephen Diamondstein
Mark Ernest Thierbach
Original Assignee
At & T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by At & T Corp filed Critical At & T Corp
Publication of SG43762A1 publication Critical patent/SG43762A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Memory System (AREA)
SG1996000664A 1993-11-16 1994-11-09 Digital processor and viterbi decoder having shared memory SG43762A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/153,405 US5432804A (en) 1993-11-16 1993-11-16 Digital processor and viterbi decoder having shared memory

Publications (1)

Publication Number Publication Date
SG43762A1 true SG43762A1 (en) 1997-11-14

Family

ID=22547091

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996000664A SG43762A1 (en) 1993-11-16 1994-11-09 Digital processor and viterbi decoder having shared memory

Country Status (6)

Country Link
US (1) US5432804A (de)
EP (1) EP0653847A3 (de)
JP (1) JP3280529B2 (de)
KR (1) KR0175340B1 (de)
SG (1) SG43762A1 (de)
TW (1) TW283219B (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656712A1 (de) * 1993-11-16 1995-06-07 AT&T Corp. Viterbi-Entzerrer mit "Traceback" variabler länge
TW243568B (en) * 1993-11-16 1995-03-21 At & T Corp Digital signal processor with an embedded viterbi co-processor
FR2724273B1 (fr) * 1994-09-05 1997-01-03 Sgs Thomson Microelectronics Circuit de traitement de signal pour mettre en oeuvre un algorithme de viterbi
US6330644B1 (en) * 1994-10-27 2001-12-11 Canon Kabushiki Kaisha Signal processor with a plurality of kinds of processors and a shared memory accessed through a versatile control means
US6327648B1 (en) * 1994-12-09 2001-12-04 Cirrus Logic, Inc. Multiprocessor system for digital signal processing
US5822341A (en) * 1995-04-06 1998-10-13 Advanced Hardware Architectures, Inc. Multiport RAM for use within a viterbi decoder
US5742621A (en) * 1995-11-02 1998-04-21 Motorola Inc. Method for implementing an add-compare-select butterfly operation in a data processing system and instruction therefor
US5802116A (en) * 1996-04-04 1998-09-01 Lucent Technologies Inc. Soft decision Viterbi decoding with large constraint lengths
US5754590A (en) * 1996-05-17 1998-05-19 Lucent Technologies, Inc. Modem architecture for integrated controller and data pump applications
US5960453A (en) 1996-06-13 1999-09-28 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
US5808573A (en) * 1996-08-01 1998-09-15 Nec Electronics Incorporated Methods and structure for sampled-data timing recovery with reduced complexity and latency
US5949820A (en) * 1996-08-01 1999-09-07 Nec Electronics Inc. Method for optimizing an equalization and receive filter
US5862154A (en) 1997-01-03 1999-01-19 Micron Technology, Inc. Variable bit width cache memory architecture
US5914989A (en) * 1997-02-19 1999-06-22 Nec Electronics, Inc. PRML system with reduced complexity maximum likelihood detector
EP0911984A1 (de) * 1997-10-21 1999-04-28 Deutsche Thomson-Brandt Gmbh Reed-Solomon Fehlerkorrektion mit einem geteilten Speicher
EP0911982A1 (de) * 1997-10-21 1999-04-28 Deutsche Thomson-Brandt Gmbh Reed-Solomon-Fehlerkorrektur mit einem gemeinsamen Speicher
GB2333014A (en) * 1997-12-31 1999-07-07 Samsung Electronics Co Ltd Virerbi equalizer using dsp's
EP0945989A1 (de) * 1998-03-12 1999-09-29 Hitachi Micro Systems Europe Limited Viterbi-Dekodierung
KR100437757B1 (ko) * 1998-12-17 2004-08-16 엘지전자 주식회사 보코더용메모리관리방법
GB0001577D0 (en) * 2000-01-24 2000-03-15 Radioscape Ltd Software for designing modelling or performing digital signal processing
AU2001291311A1 (en) * 2000-09-08 2002-03-22 Avaz Networks Programmable and multiplierless viterbi accelerator
KR100438537B1 (ko) 2001-07-19 2004-07-03 엘지전자 주식회사 이동 통신 단말기에서의 복호 장치 및 그 제어 방법
US7043682B1 (en) 2002-02-05 2006-05-09 Arc International Method and apparatus for implementing decode operations in a data processor
DE10310812B4 (de) * 2003-03-12 2007-11-22 Infineon Technologies Ag Dekodiervorrichtung, Trellis-Prozessor und Verfahren
KR100771601B1 (ko) * 2004-12-22 2007-10-31 엘지전자 주식회사 비터비 복호기를 포함한 디지털 멀티미디어 방송 수신장치
KR101064878B1 (ko) * 2005-03-17 2011-09-16 엠텍비젼 주식회사 복수의 프로세서에 의한 메모리 공유 방법 및 메모리 공유구조를 가지는 휴대형 단말기
US7752530B2 (en) * 2005-11-10 2010-07-06 Samsung Electronics Co., Ltd. Apparatus and method for a collision-free parallel turbo decoder in a software-defined radio system
US20170177435A1 (en) * 2015-12-16 2017-06-22 Cognitive Systems Corp. Sharing Memory Between Processors in a Wireless Sensor Device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536878A (en) * 1982-09-20 1985-08-20 Sperry Corporation Bit serial convolutional decoder for VLSI implementation
JPS6081925A (ja) * 1983-10-12 1985-05-10 Nec Corp 誤り訂正装置
JP2564805B2 (ja) * 1985-08-08 1996-12-18 日本電気株式会社 情報処理装置
US4730322A (en) * 1985-09-27 1988-03-08 California Institute Of Technology Method and apparatus for implementing a maximum-likelihood decoder in a hypercube network
JPS62101128A (ja) * 1985-10-29 1987-05-11 Fujitsu Ltd ビタビ復号器の試験方法
US4896264A (en) * 1986-09-08 1990-01-23 American Telephone And Telegraph Company Microprocess with selective cache memory
US5144644A (en) * 1989-10-13 1992-09-01 Motorola, Inc. Soft trellis decoding
US5193094A (en) * 1990-03-07 1993-03-09 Qualcomm Incorporated Method and apparatus for generating super-orthogonal convolutional codes and the decoding thereof
US5151904A (en) * 1990-09-27 1992-09-29 The Titan Corporation Reconfigurable, multi-user viterbi decoder
FR2669445B1 (fr) * 1990-11-15 1993-01-08 Alcatel Radiotelephone Dispositif prevu pour le traitement de l'algorithme de viterbi comprenant un processeur et un operateur specialise.
US5220570A (en) * 1990-11-30 1993-06-15 The Board Of Trustees Of The Leland Stanford Junior University Programmable viterbi signal processor
BE1004814A3 (nl) * 1991-05-08 1993-02-02 Bell Telephone Mfg Decodeerinrichting.
US5204874A (en) * 1991-08-28 1993-04-20 Motorola, Inc. Method and apparatus for using orthogonal coding in a communication system

Also Published As

Publication number Publication date
KR0175340B1 (ko) 1999-04-01
US5432804A (en) 1995-07-11
EP0653847A2 (de) 1995-05-17
KR950016066A (ko) 1995-06-17
EP0653847A3 (de) 1996-02-14
JPH07193515A (ja) 1995-07-28
TW283219B (de) 1996-08-11
JP3280529B2 (ja) 2002-05-13

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